MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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DSP56007/D
DSP56007
SYMPHONY
™
AUDIO DSP FAMILY
24-BIT DIGITAL SIGNAL PROCESSORS
Motorola designed the Symphony
™
family of high-performance, programmable Digital Signal
Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,
ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by
Motorola for integration into products like audio/video receivers, televisions, and automotive
sound systems with such user-developed features as digital equalization and sound field
processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit
Digital Signal Processor core, program and data memories, various peripherals optimized for
audio, and support circuitry. As illustrated in
Figure 1
, the DSP56000 core family compatible
DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial
Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated
I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE
™
) port. The
DSP56007 has significantly more on-chip memory than the DSP56004.
ˇ
Freescale Semiconductor, Inc...
4
General
Purpose
Input/
Output
9
Serial
Audio
Interface
(SAI)
5
Serial
Host
Interface
(SHI)
29
External
Memory
16-Bit Bus
24-Bit Bus
Interface
(EMI)
Program
Memory*
X Data
Memory*
Y Data
Memory*
24-Bit
DSP56000
Core
Internal
Data
Bus
Switch
Address
Generation
Unit
PAB
XAB
YAB
GDB
PDB
XDB
YDB
OnCE
TM
Port
Clock
Gen.
Interrupt
Control
PLL
Program
Program
Address
Decode
Generator
Controller
Program Control Unit
Data ALU
24
×
24 + 56
→
56-Bit MAC
Two 56-Bit Accumulators
3
4
4
IRQA, IRQB, NMI, RESET
*
Refer to Table 1 for memory configurations.
AA0248
Figure 1
DSP56007 Block Diagram
©1996, 1997 MOTOROLA, INC.
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Freescale Semiconductor, Inc...
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is
active when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal
is low
Means that a high true (active high) signal is low or that a low true (active low) signal
is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
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DSP56007/D
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MOTOROLA
Freescale Semiconductor, Inc.
DSP56007
Features
FEATURES
Digital Signal Processing Core
•
•
•
Efficient, object code compatible with the 24-bit DSP56000 core family engine
Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at
88 MHz
Highly parallel instruction set with unique DSP addressing modes
Two 56-bit accumulators including extension byte
Parallel 24
×
24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
Double precision 48
×
48-bit multiply with 96-bit result in 6 instruction cycles
56-bit addition/subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multiprecision arithmetic
Hardware support for block floating-point Fast Fourier Transforms (FFT)
Hardware nested DO loops
Zero-overhead fast interrupts (2 instruction cycles)
Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
Fabricated in high-density CMOS
Freescale Semiconductor, Inc...
•
•
•
•
•
•
•
•
•
•
Memory
•
•
On-chip modified Harvard architecture, which permits simultaneous accesses
to program and two data memories
Bootstrap loading from Serial Host Interface or External Memory Interface
Table 1
Memory Configuration (Word width is 24 bits)
Mode
PE
0
1
Program
ROM
6400
5120
RAM
None
1024
X Data
ROM
512
512
RAM
1024
1024
Y Data
ROM
512
512
RAM
2176
1152
Bootstrap
ROM
52
52
MOTOROLA
DSP56007/D
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Freescale Semiconductor, Inc.
DSP56007
Features
Peripheral and Support Circuits
•
Serial Audio Interface (SAI) includes two receivers and three transmitters,
master or slave capability, implementation of I
2
S, Sony, and Matsushita audio
protocols; and two sets of SAI interrupt vectors
Serial Host Interface (SHI) features single master capability, 10-word receive
FIFO, and support for 8-, 16-, and 24-bit words
External Memory Interface (EMI), implemented as a peripheral supporting:
–
Page-mode DRAMs (one or two chips): 64 K
×
4, 256 K
×
4,
and 4 M
×
4 bits
SRAMs (one to four): 256 K
×
8 bits
Data bus may be 4 or 8 bits wide
Data words may be 8, 12, 16, 20, or 24 bits wide
•
•
Freescale Semiconductor, Inc...
–
–
–
•
•
•
•
•
•
•
•
•
•
Four dedicated, independent, programmable General Purpose Input/Output
(GPIO) lines
On-chip peripheral registers memory mapped in data memory space
Three external interrupt request pins
On-Chip Emulation (OnCE) port for unobtrusive, processor speed-
independent debugging
Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
for the core clock
Power-saving Wait and Stop modes
Fully static, HCMOS design for operating frequencies down to DC
80-pin plastic Quad Flat Pack surface-mount package; 14
×
14
×
2.20 mm
(2.15–2.45 mm range); 0.65 mm lead pitch
Complete pinout compatibility between DSP56009, DSP56004,
DSP56004ROM, and DSP56007 for easy upgrades
5 V power supply
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DSP56007/D
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MOTOROLA
Freescale Semiconductor, Inc.
DSP56007
Product Documentation
PRODUCT DOCUMENTATION
Table 2
lists the documents that provide a complete description of the DSP56007 and
are required to design properly with the part. Documentation is available from a local
Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature
Distribution Center, or through the Motorola DSP home page on the Internet (the
source for the latest information).
Table 2
DSP56007 Documentation
Document Name
Description of Content
DSP56000 core family architecture and the 24-bit
core processor and instruction set
Memory, peripherals, and interfaces
Electrical and timing specifications,
and pin and package descriptions
Order Number
DSP56KFAMUM/AD
DSP56007UM/AD
DSP56007/D
Freescale Semiconductor, Inc...
DSP56000 Family
Manual
DSP56007 User’s
Manual
DSP56007 Technical
Data
MOTOROLA
DSP56007/D
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