Part Number S5320
Revision 5.03 – June 14, 2006
S5320
PCI Match Maker
FEATURES
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Full 132 Mbytes/sec Transfer Rate
PCI Bus Operation to 33 MHz
PCI 2.2 Compliant Target Device
3.3V Power Supply
5V Tolerant I/Os
Add-On Bus up to 40 MHz
Programmable Prefetch and Wait States
8/16/32-Bit Add-On Bus
Four Definable Pass-Thru Regions
Two 32-Byte Burstable FIFOs
Active/Passive Add-On Bus Operation
Mailbox Registers/w Byte Level Status
Direct Mailbox Data Strobe/Int Pin
Mailbox Read/Write Interrupts
Direct PCI and Add-On Interrupt Pins
Plug-N-Play Compatible
Two-wire Serial Bus nvRAM Support
Optional External BIOS capability
176-Pin Low Profile LQFP
Environmental Friendly Lead-free Package
Option
Data Sheet
APPLICATIONS
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ISA Conversions
Multimedia
I/O Ports
Data Storage
CODEC5
General Purpose PCI Bus Interfacing
ARCHITECTURAL OVERVIEW
The AMCC S5320 was developed to provide the
designer with a single multi-function device offering a
flexible and easy way to connect to the PCI bus. By
using the S5320, the designer eliminates the task of
assuring PCI bus specification compliance and the
necessity of understanding PCI bus timing require-
ments when interfacing a new application. The S5320
was designed for 3.3V environment but its inputs/out-
puts are tolerant to 5V signaling.
The complex 33 MHz PCI bus signals are converted
through the S5320 into an easy-to-use 8/16/32-bit
user bus referred to as the user Add-On bus. The Add-
On bus allows user add-on designs bus clock speed
independent operation to 40 MHz.
AMCC Confidential and Proprietary
DS1656
3
S5320 – PCI Match Maker
Revision 5.03 – June 14, 2006
Data Sheet
TABLE OF CONTENTS
FEATURES .............................................................................................................................................................. 3
APPLICATIONS ...................................................................................................................................................... 3
ARCHITECTURAL OVERVIEW .............................................................................................................................. 3
ARCHITECTURAL OVERVIEW S5320 ................................................................................................................. 15
S5320 REGISTER ARCHITECTURE .................................................................................................................... 15
PCI Configuration Registers ............................................................................................................................ 15
PCI Bus Accessible Registers ......................................................................................................................... 15
Add-On Bus Accessible Registers ................................................................................................................... 15
SERIAL NON-VOLATILE INTERFACE ................................................................................................................ 15
MAILBOX OPERATION ........................................................................................................................................ 17
PASS-THRU OPERATION .................................................................................................................................... 17
PCI BUS SIGNALS ............................................................................................................................................... 21
ADD-ON BUS AND S5320 CONTROL SIGNALS ................................................................................................ 23
USER ADD-ON BUS PIN DESCRIPTIONS .......................................................................................................... 24
PCI CONFIGURATIONS REGISTERS .................................................................................................................. 29
Vendor Identification Register (VID) ................................................................................................................ 29
Device Identification Register (DID) ................................................................................................................ 30
PCI Command Register (PCICMD) ................................................................................................................. 31
PCI Status Register (PCISTS) ......................................................................................................................... 33
Revision Identification Register (RID) .............................................................................................................. 35
Class Code Register (CLCD) .......................................................................................................................... 36
Cache Line Size Register (CALN) ................................................................................................................... 41
Latency Timer Register (LAT) ......................................................................................................................... 42
Header Type Register (HDR) .......................................................................................................................... 43
Built-In Self-Test Register (BIST) .................................................................................................................... 44
Base Address Register (BADR) ...................................................................................................................... 45
Determining Base Address Size ...................................................................................................................... 45
Assigning the Base Address ............................................................................................................................ 45
Subsystem Vendor Identification Register (SVID) ........................................................................................... 50
Subsystem ID Register (SID) .......................................................................................................................... 51
Expansion ROM Base Address Register (XROM) .......................................................................................... 52
Interrupt Line Register (INTLN) ....................................................................................................................... 54
Interrupt Pin Register (INTPIN) ...................................................................................................................... 55
Minimum Grant Register (MINGNT) ................................................................................................................ 56
Maximum Latency Register (MAXLAT) ........................................................................................................... 57
OPERATION REGISTERS .................................................................................................................................... 59
PCI BUS OPERATION REGISTERS .................................................................................................................... 59
PCI Outgoing Mailbox Register (OMB) ............................................................................................................ 60
PCI Incoming Mailbox Register (IMB) ............................................................................................................. 61
PCI Mailbox Empty/full Status Register (MBEF) ............................................................................................. 62
PCI Interrupt Control/Status Register (INTCSR) ............................................................................................. 63
PCI Reset Control Register (RCR) .................................................................................................................. 65
PCI Pass-Thru Configuration Register (PTCR) ............................................................................................... 67
ADD-ON BUS OPERATION REGISTERS ............................................................................................................ 69
AMCC Confidential and Proprietary
DS1656
5
Embedded System
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