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CY7C187A-20DMB

Description
Standard SRAM, 64KX1, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
Categorystorage    storage   
File Size147KB,9 Pages
ManufacturerCypress Semiconductor
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CY7C187A-20DMB Overview

Standard SRAM, 64KX1, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24

CY7C187A-20DMB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeDIP
package instruction0.300 INCH, CERDIP-24
Contacts24
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Maximum access time20 ns
Other featuresAUTOMATIC POWER-DOWN
I/O typeSEPARATE
JESD-30 codeR-GDIP-T24
JESD-609 codee0
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width1
Number of functions1
Number of ports1
Number of terminals24
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize64KX1
Output characteristics3-STATE
ExportableNO
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP22,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum standby current0.02 A
Minimum standby current4.5 V
Maximum slew rate0.09 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
CY7C187A
64K x 1 Static RAM
Features
• High speed
— 20 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 220 mW
• TTl-compatible inputs and outputs
• Automatic power-down when deselected
provided by an active LOW chip enable (CE) and three-state
drivers. The CY7C187A has an automatic power-down fea-
ture, reducing the power consumption by 55% when deselect-
ed.
Writing to the device is accomplished when the chip enable
(CE) and write enable (WE) inputs are both LOW. Data on the
input pin (DI) is written into the memory location specified on
the address pins (A
0
through A
15
).
Reading the device is accomplished by taking the chip enable
(CE) LOW, while write enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied on the address pins will appear on the data output (DO)
pin.
The output pin stays in high-impedance state when chip en-
able (CE) is HIGH or write enable (WE) is LOW.
The 7C187A utilizes a die coat to insure alpha immunity.
Functional Description
The CY7C187A is a high-performance CMOS static RAM or-
ganized as 65,536 words by 1 bit. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
D
OUT
WE
GND
1
22
2
21
3
20
4
19
5
18
6 7C187A 17
16
7
15
8
14
9
13
10
11
12
V
CC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
D
IN
CE
C187A–2
DI
INPUT BUFFER
CE
COLUMN DECODER
POWER
DOWN
WE
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
C187A–1
D
OUT
A
2
A
3
A
4
A
5
A
6
A
7
3
4
5
6
7
8
9
2 1 22 21
20
19
18
7C187A 17
16
15
14
1011 12 13
WE
GND
CE
D IN
A1
A0
VCC
A15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
C187A–3
A
12
A
13
A
14
A
15
A
0
A
1
A
2
A
3
ROW DECODER
256 x 256
ARRAY
SENSE AMPS
DO
LCC
Top View
Selection Guide
[1]
7C187A–15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Military
Military
15
160
40/20
7C187A–20
20
90
40/20
7C187A–25
25
80
40/20
7C187A–35
35
80
30/20
Shaded area contains preliminary information.
Notes:
1. For commercial specifications, see CY7C187 datasheet.
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134 •
408-943-2600
May 1986 - Revised March 1995

CY7C187A-20DMB Related Products

CY7C187A-20DMB CY7C187A-25LMB CY7C187A-15DMB CY7C187A-20LMB CY7C187A-25DMB
Description Standard SRAM, 64KX1, 20ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24 Standard SRAM, 64KX1, 25ns, CMOS, CQCC22, LCC-22 Standard SRAM, 64KX1, 15ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24 Standard SRAM, 64KX1, 20ns, CMOS, CQCC22, LCC-22 Standard SRAM, 64KX1, 25ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible
Maker Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor
Parts packaging code DIP LCC DIP LCC DIP
package instruction 0.300 INCH, CERDIP-24 LCC-22 0.300 INCH, CERDIP-24 LCC-22 0.300 INCH, CERDIP-24
Contacts 24 22 24 22 24
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant not_compliant
ECCN code 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C 3A001.A.2.C
Maximum access time 20 ns 25 ns 15 ns 20 ns 25 ns
Other features AUTOMATIC POWER-DOWN AUTOMATIC POWER-DOWN AUTOMATIC POWER-DOWN AUTOMATIC POWER-DOWN AUTOMATIC POWER-DOWN
I/O type SEPARATE SEPARATE SEPARATE SEPARATE SEPARATE
JESD-30 code R-GDIP-T24 R-CQCC-N22 R-GDIP-T24 R-CQCC-N22 R-GDIP-T24
JESD-609 code e0 e0 e0 e0 e0
memory density 65536 bit 65536 bit 65536 bit 65536 bit 65536 bit
Memory IC Type STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM
memory width 1 1 1 1 1
Number of functions 1 1 1 1 1
Number of ports 1 1 1 1 1
Number of terminals 24 22 24 22 24
word count 65536 words 65536 words 65536 words 65536 words 65536 words
character code 64000 64000 64000 64000 64000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C -55 °C
organize 64KX1 64KX1 64KX1 64KX1 64KX1
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Exportable NO NO NO NO NO
Package body material CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED
encapsulated code DIP QCCN DIP QCCN DIP
Encapsulate equivalent code DIP22,.3 LCC22,.3X.5 DIP22,.3 LCC22,.3X.5 DIP22,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE CHIP CARRIER IN-LINE CHIP CARRIER IN-LINE
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 5 V 5 V 5 V 5 V 5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Filter level 38535Q/M;38534H;883B 38535Q/M;38534H;883B 38535Q/M;38534H;883B 38535Q/M;38534H;883B 38535Q/M;38534H;883B
Maximum standby current 0.02 A 0.02 A 0.02 A 0.02 A 0.02 A
Minimum standby current 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Maximum slew rate 0.09 mA 0.08 mA 0.16 mA 0.09 mA 0.08 mA
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V
surface mount NO YES NO YES NO
technology CMOS CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE NO LEAD THROUGH-HOLE NO LEAD THROUGH-HOLE
Terminal pitch 2.54 mm 1.27 mm 2.54 mm 1.27 mm 2.54 mm
Terminal location DUAL QUAD DUAL QUAD DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
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