a
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V
P
) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
200 MHz Clock Generator PLL
ADF4001
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REF
IN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an exter-
nal loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DV
DD
V
P
CPGND
R
SET
ADF4001
REF
IN
14-BIT
R COUNTER
14
R COUNTER
LATCH
CLK
DATA
LE
SD
OUT
24-BIT
INPUT REGISTER
22
FUNCTION
LATCH
LOCK DETECT
REFERENCE
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2
CPI1 CPI6 CPI5
CPI4
N COUNTER
LATCH
13
AV
DD
MUX
13-BIT
N COUNTER
SD
OUT
HIGH Z
MUXOUT
RF
IN
A
RF
IN
B
M3
M2
M1
REV.
B
CE
AGND
DGND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax:
781/461-3113
©
2013
Analog Devices, Inc. All rights reserved.
(AV
DD
= DV
DD
= 3 V 10%, 5 V 10%; AV
DD
≤
V
P
≤
6.0 V ; AGND = DGND =
CPGND = 0 V; R
SET
= 4.7 k ; T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm referred to 50 .)
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency
RF Input Sensitivity
RF CHARACTERISTICS (5 V)
RF Input Frequency
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
REF
IN
Input Sensitivity
2
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
3
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage Current
Sink and Source Current Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
V
P
I
DD4
(AI
DD
+ DI
DD
)
ADF4001
I
P
Low Power Sleep Mode
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor
5
Phase Noise Performance
6
200 MHz Output
7
Spurious Signals
200 MHz Output
7
B Version
5/165
–10/0
10/200
20/200
5/104
–5
10
±
100
55
Unit
MHz min/max
dBm min/max
MHz min/max
MHz min/max
MHz min/max
dBm min
pF max
µA
max
MHz max
Programmable: See Table V
With R
SET
= 4.7 kΩ
With R
SET
= 4.7 kΩ
See Table V
0.5 V
≤
V
CP
≤
V
P
– 0.5
0.5 V
≤
V
CP
≤
V
P
– 0.5
V
CP
= V
P
/2
–5/0 dBm min/max
–10/0 dBm min/max
See Figure 2 for Input Circuit
For f < 5 MHz, Use DC-Coupled Square Wave
(0 to V
DD
)
AC-Coupled. When DC-Coupled:
0 to V
DD
Max (CMOS Compatible)
Test Conditions/Comments
See Figure 3 for Input Circuit
ADF4001–SPECIFICATIONS
1
5
625
2.5
2.7/10
1
2
1.5
2
0.8
×
DV
DD
0.2
×
DV
DD
±
1
10
DV
DD
– 0.4
0.4
2.7/5.5
AV
DD
AV
DD
/6.0
5.5
0.4
1
–161
–153
–99
–90/–95
mA typ
µA
typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
V min
V max
µA
max
pF max
V min
V max
V min/V max
V min/V max
mA max
mA max
µA
typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ/dBc typ
I
OH
= 500
µA
I
OL
= 500
µA
AV
DD
≤
V
P
≤
6.0 V
4.5 mA typical
T
A
= 25°C
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ VCXO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1
Operating temperature range (B Version) is –40°C to +85°C.
2
AV
DD
= DV
DD
= 3 V; for AV
DD
= DV
DD
= 5 V, use CMOS compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; RF
IN
= 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset Frequency = 1 kHz; f
RF
= 200 MHz; N = 1000; Loop B/W = 20 kHz.
Specifications subject to change without notice.
–2–
REV.
B
ADF4001
TIMING CHARACTERISTICS
(AV
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
DV
DD
= 3 V 10%, 5 V
R
SET
= 4.7 k ; T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm referred to 50
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
DD
=
10%; AV
DD
≤
V
P
≤
6.0 V ; AGND = DGND = CPGND= 0 V;
.)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
Guaranteed by design but not production tested.
Specifications subject to change without notice.
t
3
CLOCK
t
4
t
1
DATA
DB20
(MSB)
DB19
t
2
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(
T
A
= 25°C, unless otherwise noted.)
AV
DD
to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +0.3 V
V
P
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
to AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
RF
IN
A to RF
IN
B . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
600
mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . 150°C
TSSOP
θ
JA
Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W
LFCSP
θ
JA
Thermal Impedance (Paddle Soldered) . . 122°C/W
LFCSP
θ
JA
Thermal Impedance (Paddle Not Soldered) 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
<2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = AGND = DGND = 0 V.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV.
B
–3–
ADF4001
PIN CONFIGURATIONS
R
SET
CP
CPGND
AGND
RF
IN
B
1
2
3
4
5
16
V
P
15
DV
DD
14
MUXOUT
20
19
18
17
16
CP
R
SET
V
P
DV
DD
DV
DD
ADF4001
TOP VIEW
(Not to Scale)
13
LE
12
DATA
11
CLK
10
CE
9
RF
IN
A
6
AV
DD
7
CPGND
AGND
AGND
RF
IN
B
RF
IN
A
1
2
3
4
5
ADF4001
TOP VIEW
(Not to Scale)
15
14
13
12
11
MUXOUT
LE
DATA
CLK
CE
TSSOP
LFCSP
Table 1. Pin Function Descriptions
TSSOP
Pin No.
1
LFCSP
Pin No.
19
Mnemonic
R
SET
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship
between I
CP
and R
SET
is
I
CP MAX
½
23.5
R
SET
2
3
4
5
6
7
20
1
2, 3
4
5
6, 7
CP
CPGND
AGND
RF
IN
B
RF
IN
A
AV
DD
8
8
REF
IN
9
10
9, 10
11
DGND
CE
11
12
CLK
12
13
14
15
13
14
15
16, 17
DATA
LE
MUXOUT
DV
DD
16
18
V
P
N/A
EP
EPAD
So, with R
SET
= 4.7 kΩ, I
CP MAX
= 5 mA.
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter which,
in turn, drives the external VCO or VCXO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the N counter. This point must be decoupled to the ground
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
DD
must have the
same value as DV
DD
.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DV
DD
must be the
same value as AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems
where V
DD
is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
range of up to 5 V.
Exposed Pad. The exposed pad should be connected to AGND.
Rev. B | Page 4
02569-004
NOTES
1. TRANSISTOR COUNT 6425 (CMOS)
AND 50 (BIPOLAR).
02569-003
NOTES
1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).
2. CONNECT EXPOSED PAD TO AGND.
AV
DD
6
7
AV
DD
REF
IN
8
DGND
9
DGND
10
REF
IN
8
DGND
Typical Performance Characteristics–ADF4001
0
–5
10dB/DIVISION
–40
–50
–60
R
L
= –40dBc/Hz
rms NOISE = 0.229 DEGREES
0.229 rms
–10
AMPLITUDE – dBm
PHASE NOISE – dBc/Hz
–70
–80
–90
–100
–110
–120
–15
T
A
= +85 C
–20
T
A
= +25 C
–25
–30
T
A
= –40 C
–35
0
50
100
150
FREQUENCY – MHz
200
250
–130
–140
100
1k
10k
100k
FREQUENCY OFFSET FROM 200MHz CARRIER – Hz
1M
TPC 1. Input Sensitivity, V
DD
= 3.3 V, 100 pF on RF
IN
TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)
0
0
–10
V
DD
= 3V, V
P
= 5V
I
CP
= 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 300Hz
VIDEO BANDWIDTH = 300Hz
SWEEP = 4.2 SECONDS
AVERAGES = 20
–5
OUTPUT POWER – dB
–20
–30
–40
–50
–60
–70
–80
–90
REFERENCE LEVEL =
–5.7dBm
AMPLITUDE – dBm
–10
–15
–20
–92.3dBc
–25
–30
0
5
10
15
FREQUENCY – MHz
20
25
–100
–200kHz
–100kHz
200MHz
100kHz
200kHz
0
TPC 2. Input Sensitivity, V
DD
= 3.3 V, 100 pF on RF
IN
TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz)
0
–10
–20
OUTPUT POWER – dB
REFERENCE LEVEL =
–5.7dBm
–30
–40
–50
–60
–70
V
DD
= 3V, V
P
= 5V
I
CP
= 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 26
–99.2dBc/Hz
–80
–90
–100
–2kHz
–1kHz
200MHz
1kHz
2kHz
0
TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz)
REV.
B
–5–
stm32/stm8
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