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M2004-32-622.0800LF

Description
PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36
Categorylogic    logic   
File Size291KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

M2004-32-622.0800LF Overview

PLL Based Clock Driver, 2004 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M2004-32-622.0800LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instructionQCCN,
Contacts36
Reach Compliance Codecompliant
series2004
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-CQCC-N36
JESD-609 codee3
length8.99 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals36
Actual output times1
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height3.1 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formNO LEAD
Terminal pitch0.635 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width8.99 mm
minfmax700 MHz
Integrated
Circuit
Systems, Inc.
Preliminary Information
M2004-x2
*
F
REQUENCY
T
RANSLATION
PLL F
AMILY
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
M0
GND
REF_CLK
DIF_REF
nDIF_REF
REF_SEL
NC
NC
VCC
M1
M2
M3
M4
M5
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2004 variants -22, -32, -42, and -52 are VCSO
(Voltage Controlled SAW Oscillator)
based clock generator PLLs
designed for clock frequency
translation and jitter attenuation in
a high-speed data communications
system. The clock multiplication
ratio and output divider ratio are
pin selectable. External loop components allow the
tailoring of PLL loop response. Based on the M2004-02,
these device variants add the Hitless Switching with
Phase Build-out (HS/PBO) feature. HS/PBO ensures
that reference clock reselection does not disrupt the
output clock. In addition, a fixed Narrow Loop
Bandwidth feature (Fixed NBW) is included in the some
of the device variants.
28
29
30
31
32
33
34
35
36
M2004-x2
(Top View)
18
17
16
15
14
13
12
11
10
NC
MR
nFOUT
FOUT
GND
N1
N0
VCC
GND
F
EATURES
Pin-compatible with M2004-02/-12, these new product
variants offer new functions
Hitless Switching with Phase Build-out to ensure
SONET/SDH MTIE and TDEV compliance during
reference clock reselection
Fixed Narrow Loop Bandwidth feature available
Ideal for OC-48/192 data clock
Integrated SAW (surface acoustic wave) delay line
VCSO frequency from 300 to 700MHz
**
Low phase jitter of < 0.5ps rms, typical
(12kHz to 20MHz or 50kHz to 80MHz)
Pin-selectable configuration
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input (MHz) VCSO ** (MHz) Output (MHz)
19.44
77.76
622.08
77.76
311.04
155.52
622.08
Application
OC-12 / 48
/192
Table 1: Example Input / Output Frequency Combinations
Device Variants and Corresponding Functions
Hitless Switching /
Phase Build-out Triggered by
Phase Transient Mux Reselection
M2004-02
no
no
M2004-12
Yes
Yes
M2004-22
no
no
M2004-32
Yes
Yes
M2004-42
no
Yes
M2004-52
no
Yes
Variant
Fixed
NBW
no
no
Yes
Yes
no
Yes
Table 2: Device Variants and Corresponding Functions
* This sheet covers only parts numbered M2004-22, -32, -42, -52.
See M2004-02/-12 Product Data Sheet
for M2004-02 & M2004-12.
** Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
M2004-x2
DIF_REF
nDIF_REF
REF_CLK
REF_SEL
M Divider
N Divider
6
M5:0
2
N1:0
FOUT
nFOUT
0
1
Loop
Filter
VCSO
Figure 2: Simplified Block Diagram
M2004-x2 Datasheet Rev 1.3
M2004-x2 Frequency Translation PLL Family
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
MR
Revised 10Sep2003
Integrated Circuit Systems, Inc.
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