24LCS52
2K 2.2V I
2
C
™
Serial EEPROM with Software Write Protect
FEATURES
• Single supply with operation down to 2.2V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as a single block of 256 bytes (256 x 8)
• Software write protection for lower 128 bytes
• Hardware write protection for entire array
• 2-wire serial interface bus, I
2
C™ compatible
• 100kHz (2.2V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 3.5 ms typical write cycle time for page-write
• 1,000,000 erase/write cycles guaranteed
• ESD protection >4,000V
• Data retention > 200 years
• 8-pin DIP, SOIC or TSSOP packages
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
PACKAGE TYPES
PDIP/SOIC
A0
A1
A2
Vss
1
8
Vcc
WP
SCL
SDA
24LCS52
2
3
4
7
6
5
TSSOP
A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
24LCS52
DESCRIPTION
The Microchip Technology Inc. 24LCS52 is a 2K bit
Electrically Erasable PROM capable of operation
across a broad voltage range (2.2V to 5.5V). This
device has a software write protect feature for the lower
half of the array, as well as an external pin that can be
used to write protect the entire array. The software write
protect feature is enabled by sending the device a spe-
cial command, and once this feature has been enabled,
it cannot be reversed. In addition to the software pro-
tect feature, there is a WP pin that can be used to write
protect the entire array, regardless of whether the soft-
ware write protect register has been written or not. This
allows the system designer to protect none, half or all
of the array, depending on the application. The device
is organized as a single block of 256 x 8-bit memory
with a 2-wire serial interface. Low voltage design per-
mits operation down to 2.2 volts with typical standby
and active currents of only 5 µA and 1 mA respectively.
The device has a page-write capability for up to 16
bytes of data. The device is available in the standard 8-
pin DIP, 8-pin SOIC and TSSOP packages.
BLOCK DIAGRAM
A0 A1 A2
WP
HV Generator
Software write
protected area
(00h-7Fh)
Standard
Array
SDA SCL
Vcc
Vss
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
I/O
Control
Logic
Memory
Control
Logic
XDEC
I
2
C is a trademark of Philips Corporation.
©
1999 Microchip Technology Inc.
DS21166E-page 1
24LCS52
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
V
SS
SDA
SCL
V
CC
A0, A1, A2
WP
PIN FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock
+2.2V to 5.5V Power Supply
Chip Selects
Hardware Write Protect
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins............................................ Š 4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +2.2V to +5.5V
Parameter
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CC
Read
I
CCS
Min.
.7 V
CC
.3 V
CC
—
.40
10
50
10
10
3
1
30
100
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I): Tamb = -40°C to +85°C
Max.
Units
V
V
V
V
µA
µA
µA
pF
mA
mA
µA
µA
Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
Input leakage current
All I/O pins
WP pin
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
.05 V
CC
(Note)
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= 0.1V to 5.5V, WP = Vss
WP = V
CC
V
OUT
= 0.1V to 5.5V
V
CC
= 5.0V (Note)
Tamb = 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
WP = V
SS
, A0, A1, A2 = V
SS
-10
-10
-10
—
—
—
—
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
START
STOP
DS21166E-page 2
©
1999 Microchip Technology Inc.
24LCS52
TABLE 1-3:
AC CHARACTERISTICS
Vcc = 2.2-5.5V
STD MODE
Min.
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Vcc = 4.5 - 5.5V
FAST MODE
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
Units
Remarks
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
T
OF
T
SP
T
WR
—
—
—
1M
250
50
10
—
20 +0.1
CB
—
—
1M
250
50
10
—
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), CB ð 100 pF
(Note 3)
ms
Byte or Page mode
cycles 25°C, V
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
SP
T
AA
SDA
OUT
T
HD
:
STA
T
AA
T
BUF
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
©
1999 Microchip Technology Inc.
DS21166E-page 3
24LCS52
2.0
FUNCTIONAL DESCRIPTION
The 24LCS52 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LCS52
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5
Acknowledge
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LCS52 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.6
Device Addressing
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
A control byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit control code which
is set to 1010 for normal read and write operations and
0110 for writing to the write protect register. The control
byte is followed by three chip select bits (A2, A1, A0).
The chip select bits allow the use of up to eight
24LCS52 devices on the same bus and are used to
determine which device is accessed. The chip select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if
you attempt a read command with the control code set
to 0110.
FIGURE 3-1:
(A)
SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(B)
(D)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21166E-page 4
©
1999 Microchip Technology Inc.
24LCS52
The eighth bit of slave address determines if the master
device wants to read or write to the 24LCS52 (Figure 3-
2). When set to a one a read operation is selected and
when set to a zero a write operation is selected.
Operation
Read
Write
Set Write Protect
Register
Control
Code
1010
1010
0110
Chip
Select
A2 A1 A0
A2 A1 A0
A2 A1 A0
R/W
1
0
0
another acknowledge signal from the 24LCS52 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS52
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and
during this time the 24LCS52 will not generate
acknowledge signals (Figure 4-1). If an attempt is
made to write to the array when the software or hard-
ware write protection has been enabled, the device will
acknowledge the command but no data will be written.
The write cycle time must be observed even if the write
protection is enabled.
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
4.2
Page Write
1
0
1
0
OR
A2
A1
A0
0
1
1
0
A2
A1
A0
4.0
4.1
WRITE OPERATIONS
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LCS52. After receiving
The write control byte, word address and the first data
byte are transmitted to the 24LCS52 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 15 additional data
bytes to the 24LCS52 which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the four lower order
address pointer bits are internally incremented by one.
The higher order four bits of the word address remains
constant. If the master should transmit more than 16
bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2). If an attempt is
made to write to the array when the hardware write pro-
tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.
Note:
Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
©
1999 Microchip Technology Inc.
DS21166E-page 5
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