HD74CDCF2509BT datasheet, PDF - EEWORLD Datasheet

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HD74CDCF2509BT: DescriptionCDCF SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, TTP-24DB; Categorylogic logic; File Size45KB，11 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HD74CDCF2509BT Overview

CDCF SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, TTP-24DB

HD74CDCF2509BT Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	TSSOP,
Contacts	24
Reach Compliance Code	unknown
series	CDCF
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G24
length	7.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	24
Actual output times	9
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm

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HD74CDCF2509B

140 MHz, 0 to 85°C Operation

3.3-V Phase-lock Loop Clock Driver

ADE-205-224G (Z)

8th. Edition

June 2000

Description

The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a

phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the

clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

HD74CDCF2509B operates at 3.3 V V

and is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input

clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.

Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the

G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the

outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the HD74CDCF2509B does not require external RC networks.

The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDCF2509B requires a stabilization time to achieve phase lock

of the feedback signal to the reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL

reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

Features

•

Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”

•

Phase-lock loop clock distribution for synchronous DRAM applications

External feedback (FBIN) pin is used to synchronize the outputs to the clock input

No external RC network required

Support spread spectrum clock (SSC) synthesizers

Supports frequencies up to 140 MHz

0 to 85°C operating range

HD74CDCF2509BT Related Products

	HD74CDCF2509BT	HD74CDC2509BT
Description	CDCF SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, TTP-24DB	CDC SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, TTP-24DB
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	SOIC	SOIC
package instruction	TSSOP,	TSSOP,
Contacts	24	24
Reach Compliance Code	unknown	compliant
series	CDCF	CDC
Input adjustment	STANDARD	STANDARD
JESD-30 code	R-PDSO-G24	R-PDSO-G24
length	7.8 mm	7.8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1
Number of terminals	24	24
Actual output times	9	9
Maximum operating temperature	85 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	OTHER	OTHER
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
width	4.4 mm	4.4 mm

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