K7A163600M
K7A161800M
Document Title
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial draft
1. Update ICC & ISB values.
1. Change I
SB
value from 150mA to 110mA at -67.
2. Change I
SB
value from 130mA to 90mA at -72 .
3. Change I
SB
value from 120mA to 80mA at -10 .
1. Add tCYC 167MHz and 183MHz.
2. Changed DC condition at Icc and parameters
Icc ; from 420mA to 400mA at -67,
from 400mA to 380mA at -72,
from 350mA to 320mA at -10,
1. Final Spec Release.
Draft Date
Dec. 29. 1998
May. 27. 1999
Sep. 04. 1999
Remark
Preliminary
Preliminary
Preliminary
0.3
Nov. 19. 1999
Preliminary
1.0
Dec. 08. 1999
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
December 1999
Rev 1.0
K7A163600M
K7A161800M
512Kx36 & 1Mx18 Synchronous SRAM
512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
GENERAL DESCRIPTION
The K7A163600M and K7A161800M are 18,874,368-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 512K(1M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache control-
ler(ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system′s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A163600M and K7A161800M are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP and 119BGA package. Multiple
power and ground pins are utilized to minimize ground
bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -18 -16 -15 -14 -10 Unit
t
CYC
t
CD
t
OE
5.4 6.0 6.7 7.2 10
3.3 3.5 3.8 4.0 4.5
3.3 3.5 3.8 4.0 4.5
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
A′
0
~A′
1
512Kx36 , 1Mx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-2-
December 1999
Rev 1.0
Microchip MCU
京公网安备 11010802033920号
EEWORLD
