512Mb M-die DDR-II SDRAM
Target
512Mb M-die DDR-II SDRAM Specification
Version 0.11
Rev. 0.11 (Apr. 2002)
Page 1 of 66
512Mb M-die DDR-II SDRAM
Target
Contents
1. Key Feature
2. Package Pinout & Addressing
2.1 Package Pintout
2.2 Input/Output Function Description
2.3 Addressing
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
3.2.1 Power-Up Sequence
3.2.2 Programming the Mode Register
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.2.3 OCD Impedance Adjustment-Protocol
3.2.2.4 ODT (On-die termination)
3.2.3 Bank Activate Command
3.2.4 Read and write Access Modes
3.2.4.1 Posted CAS
3.2.4.2 4 bit or 8 bit Burst Mode Operation
3.2.4.3 Burst Read Command
3.2.4.4 Burst write Operation
3.2.4.5 Write data mask
3.2.5 Precharge Command
3.2.6 Auto-Precharge operation
3.2.7 Refresh Command
3.2.8 Self Refresh Command
3.2.9
4. Command Truth Table
5. Absolute Maximum Rating
6. AC & DC Operating Conditions & Specifications
Rev. 0.11 (Apr. 2002)
Page 2 of 66
512Mb M-die DDR-II SDRAM
Revision History
Version 0.0 (Feb, 2002)
Target
- Initial Release
Version 0.1 (Mar, 2002)
Corrected the typo
Add FBGA package dimension
Delete SS800 AC parameter table
Changed the CAS Latency & Additive Latency
CAS Latency : removed CL=2(Optional) and changed CL=5(Optional) to CL=5 & Added CL=6(Optional)
Additive Latency : Changed AL=4(Optional) to AL=4 & Added AL=5
- Delete tHZ min
- tIH/tIS for DDR533 : min 500ps(from TBD)
- tRRD : differentiate 1KB & 2KB page size as 7.5ns & 10ns each
- tWTR : Changed to analog value(400Mbps : 10ns, 533Mbps + : 7.5ns)
Version 0.11 (April, 2002)
-
-
-
-
- Corrected the typo
- Changed Additive Latency definition as below
Old : AL=0(Default), 1,2,3,4 and 5
New : AL=0,1,2,3 and 4
- Added Comment of Max. Package dimension
Maximum Package Height : 21mm
Maximum Package Center to Center spacing : 12.8mm
Rev. 0.11 (Apr. 2002)
Page 3 of 66
512Mb M-die DDR-II SDRAM
General Information
Organization
128Mx4
DDR400 w/ CL=4
K4T51043QM-GCD4
K4T51043QM-GLD4
64Mx8
K4T51083QM-GCD4
K4T51083QM-GLD4
32Mx16
K4T51163QM-GCD4
K4T51163QM-GLD4
DDR400 w/ CL=3
K4T51043QM-GCC4
K4T51043QM-GLC4
K4T51083QM-GCC4
K4T51083QM-GLC4
K4T51163QM-GCC4
K4T51163QM-GLC4
DDR533 w/ CL=5
K4T51043QM-GCE5
K4T51043QM-GLE5
K4T51083QM-GCE5
K4T51083QM-GLE5
K4T51163QM-GCE5
K4T51163QM-GLE5
Target
DDR533 w/ CL=4
K4T51043QM-GCD5
K4T51043QM-GLD5
K4T51083QM-GCD5
K4T51083QM-GLD5
K4T51163QM-GCD5
K4T51163QM-GLD5
1
2
3
4
5
6
7
8
9
10
11
K 4 T XX XX X X X - X X XX
Memory
DRAM
Temperature & Power
Small Classification
Density and Refresh
Organization
Bank
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
T
:
DDR-II SDRAM
4. Density & Refresh
51
:
512M 8K/64ms
8. Version
M
A
B
C
D
E
:
1st Generation
:
2nd Generation
:
3rd Generation
:
4th Generation
:
5th Generation
:
6th Generation
Package
Version
Interface (VDD & VDDQ)
Speed
9. Package
G
:
FBGA
5. Organization
04
:
x4
08
:
x8
16
:
x16
10. Temperature & Power
C :
(Commercial, Normal)
L :
(Commercial, Low)
11. Speed
6. Bank
3
:
4 Bank
7. Interface (VDD & VDDQ)
Q: SSTL-18(1.8V, 1.8V)
C4
:
5ns@CL3
D4
:
5ns@CL4
E4
:
5ns@CL5
D6
:
3ns@CL4
E6
:
3ns@CL5
F6
:
3ns@CL6
C5
:
3.75ns@CL3
D5
:
3.75ns@CL4
E5
:
3.75ns@CL5
Rev. 0.11 (Apr. 2002)
Page 4 of 66
512Mb M-die DDR-II SDRAM
1.Key Features
DDR400 DDR400 DDR533 DDR533
CL=4
CL=3
CL=5
CL=4
f
C K
Clock Frequency
Data Rate
200
400
200
400
267
533
267
533
Target
Units
MHz
Mb/s/pin
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin & 267MHz f
CK
for 533Mb/sec/pin
• 4 Bank
• Posted CAS
• Programmable CAS Latency: 3, 4, 5 and 6(Optional)
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 (Read/Write Interrupt Prohibited but only Read interrupted by Read & Write interrupted by
Write are allowed), 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Data-Strobes: Bidirectional, (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• Auto Refresh (CBR) and Self Refresh
Refesh Period 7.8us (8192 refresh cycles/64ms)
• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA - 32Mx16
Rev. 0.11 (Apr. 2002)
Page 5 of 66