SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
TM
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20894-5E
FLASH MEMORY
CMOS
32 M (4 M
×
8/2 M
×
16) BIT
MBM29LV320TE
80/90/10
MBM29LV320BE
80
/
90
/
10
■
DESCRIPTION
The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words
of 16 bits each. The device is offered in a 48-pin TSOP (1) and 63-ball FBGA packages. This device is designed
to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required
for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microproces-
sors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE)
and output enable (OE) controls.
(Continued)
MBM29LV320TE/BE
80
V
CC
=
3.3 V
+0.3
V
−0.3
V
80
80
30
90
90
35
90
100
V
CC
=
3.0 V
+0.6
V
−0.3
V
100
100
35
■
PRODUCT LINE UP
Part No.
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
■
PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
63-ball plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-63P-M01)
(Continued)
Retired Product DS05-20894-5E_July 31, 2007
MBM29LV320TE/BE
80/90/10
The device is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written to the
command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This invokes the Embedded Program
Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper
cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished
by executing the erase command sequence. This invokes the Embedded Erase Algorithm which is an internal
algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin.
A sector is Typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle is completed,
the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the
Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode
and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels of
quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a
time using the EPROM programming mechanism of hot electron injection.
Retired Product DS05-20894-5E_July 31, 2007
5
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