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A3P1000-FGG256C

Description
Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PBGA256, 1 MM PITCH, GREEN, FBGA-256
CategoryProgrammable logic devices    Programmable logic   
File Size3MB,192 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance
Download Datasheet Parametric View All

A3P1000-FGG256C Overview

Field Programmable Gate Array, 24576 CLBs, 1000000 Gates, 350MHz, CMOS, PBGA256, 1 MM PITCH, GREEN, FBGA-256

A3P1000-FGG256C Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrosemi
package instructionBGA,
Reach Compliance Codecompliant
maximum clock frequency350 MHz
JESD-30 codeS-PBGA-B256
JESD-609 codee1
length17 mm
Humidity sensitivity level3
Configurable number of logic blocks24576
Equivalent number of gates1000000
Number of terminals256
Maximum operating temperature70 °C
Minimum operating temperature
organize24576 CLBS, 1000000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)250
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.8 mm
Maximum supply voltage1.575 V
Minimum supply voltage1.425 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width17 mm
v2.0
Automotive ProASIC
®
3 Flash Family FPGAs
with Grade 2 and Grade 1 AEC-Q100 Support
Features and Benefits
High-Temperature AEC-Q100–Qualified Devices
Grade 2 105°C T
A
(115°C T
J
)
Grade 1 125°C T
A
(135°C T
J
)
PPAP Documentation
Only Automotive FPGAs to Offer Firm-Error Immunity
Can Be Used Without Configuration Upset Risk
60 k to 1 Million System Gates
Up to 144 kbits of SRAM
Up to 300 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
1 kbit of FlashROM with Synchronous Interface
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–
compliant)
FlashLock
®
to Secure FPGA Contents (anti-tampering)
®
Low Power
1.5 V Core Voltage
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and A3P1000)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the Automotive
ProASIC3 Family
Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 350 MHz)
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,
×4, ×9, and ×18 Organizations Available)
High-Performance Routing Hierarchy
Firm-Error Immune
High Capacity
Advanced I/O
Reprogrammable Flash Technology
On-Chip User Nonvolatile Memory
High Performance
In-System Programming (ISP) and Security
Clock Conditioning Circuit (CCC) and PLL
SRAMs
Table 1 •
Automotive ProASIC3 Product Family
A3P060
60 k
1,536
18
4
1k
Yes
1
18
2
96
VQ100
FG144
ProASIC3 Devices
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals*
I/O Banks
Maximum User I/Os
Package Pins
VQFP
FBGA
A3P125
125 k
3,072
36
8
1k
Yes
1
18
2
133
VQ100
FG144
A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
VQ100
FG144, FG256
A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
300
FG144, FG256, FG484
Note:
*Six chip-wide (main) globals and three additional global networks in each quadrant are available.
August 2007
© 2007 Actel Corporation
i
See the Actel website for the latest version of the datasheet.

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