700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY
SYNTHESIZER w/FANOUT BUFFER
ICS84314-02
General Description
The ICS84314-02 is a general purpose quad output
frequency synthesizer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. When the device uses parallel
loading, the M bits are programmable and the output
divider is hard-wired for divide by 2 thus providing a frequency
range of 125MHz to 350MHz. In serial programming mode, the M
bits are programmable and the output divider can be set for either
divide by 1, 2, 4 or divide by 8, providing a frequency range of
31.25MHz to 700MHz. Additionally, the device supports spread
spectrum clocking (SSC) for minimizing Electromagnetic Interfer-
ence (EMI). The low cycle-cycle jitter and broad frequency range
of the ICS84314-02 make it an ideal clock generator for a variety
of demanding applications which require high performance.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL
Four differential 3.3V or 2.5V LVPECL output pairs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK input
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel interface for programming M dividers
Supports Spread Spectrum Clocking (SSC)
Down spread: -0.6%
Serial 3 wire interface
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 40ps (maximum)
Output duty cycle: 47% – 53%
Full 3.3V or mixed 3.3V core, 2.5V output operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
VCO_SEL
PU
XTAL_SEL
PU
TEST_CLK
PD
XTAL_IN
OSC
XTAL_OUT
÷
16
1
0
Pin Assignment
VCO_SEL
nP_LOAD
XTAL_OUT
XTAL_IN
M3
M2
M1
M0
32 31 30 29 28 27 26 25
M4
M5
M6
M7
1
2
3
4
5
6
7
8
9
Q0
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nQ2
Q3
nQ0
nQ1
nQ3
Q1
Q2
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
V
CCO
PLL
PHASE DETECTOR
MR
PD
VCO
0
1
÷
M
÷
2
Output Divider N
÷1
÷2
(Power-up Default)
÷4
÷8
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
M8
V
EE
V
CC
V
CCO
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
PD
PD
PD
PD
CONFIGURATION
INTERFACE
LOGIC
ICS84314-02
32 Lead LQFP
Y Package
7mm x 7mm x 1.4mm package body
Top View
NOTE:
Pullup (PU) and Pulldown (PD)
refer to internal input resistors.
See Table 2,
Pin Characteristics,
for typical values.
IDT™ / ICS™
3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
1
ICS84314AY-02 REV. A MARCH 24, 2009
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Functional Description
NOTE:
The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The ICS84314-02 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior
to the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 700MHz. The output of the M divider is also applied to
the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS84314-02 support two input
modes to program the M divider. The two input operational modes
are parallel and serial.
Figure 1
shows the timing diagram for each
mode. In parallel mode, the nP_LOAD input is initially LOW. The
data on inputs M0 through M8 is passed directly to the M divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a result,
the M bits can be hardwired to set the M divider to a specific default
state that will automatically occur during power-up. In parallel
mode, the N output divider is set to 2. In serial mode, the N output
divider can be set for either
÷1, ÷2, ÷4
or
÷8.
The relationship
between the VCO frequency, the crystal frequency and the M
divider is defined as follows: fVCO = fXTAL x 2M
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz reference
are defined as 125
≤
M
≤
350. The frequency out is defined as
follows: fout = fVCO x 1 = fXTAL x 2M x 1
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly
to the M divider and N output divider on each rising edge of
S_CLOCK.
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
X
S
X
t
H
SSC
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8
nP_LOAD
t
S
M
t
H
S_LOAD
Time
Figure 1. Parallel Load Operations
NOTE: X = Don’t Care
N1 and N0 divider settings are only accessible through the serial configuration interface.
IDT™ / ICS™
3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
2
ICS84314AY-02 REV. A MARCH 24, 2009
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2, 5,
29, 30, 31
3, 4, 32
6
7
8, 17
9, 10
11, 12
13, 14
15, 16
Name
M4, M5, M8
M0, M1, M2
M6, M7, M3
V
EE
V
CC
V
CCO
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Input
Input
Power
Power
Power
Output
Output
Output
Output
Type
Pulldown
Pullup
Negative supply pin.
Core supply pin.
Output supply pins.
Differential clock outputs for the synthesizer. LVPECL interface levels.
Differential clock outputs for the synthesizer. LVPECL interface levels.
Differential clock outputs for the synthesizer. LVPECL interface levels.
Differential clock outputs for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Assertion
of MR does not affect loaded M values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
Pulldown
Selects between the crystal oscillator or test clock as the PLL reference
source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels. See Table 3F.
Single-ended test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is an oscillator input, XTAL_OUT is an
oscillator output.
Pulldown
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded into the
M divider. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels. See Table 3G.
Description
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
18
MR
Input
Pulldown
19
20
21
22
23
24
25,
26
27
28
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
TEST_CLK
XTAL_IN,
XTAL_OUT
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
IDT™ / ICS™
3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
3
ICS84314AY-02 REV. A MARCH 24, 2009
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces Qx outputs LOW, nQx outputs HIGH.
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input does not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE:L = LOW
H = HIGH
X = Don’t care
↑
= Rising edge transition
↓
= Falling edge transition
Table 3B. Programmable VCO Frequency Function Table (NOTE 1)
VCO Frequency
(MHz)
250
252
254
256
•
•
696
698
700
256
M Divide
125
126
127
128
•
•
348
349
350
M8
0
0
0
0
•
•
1
1
1
128
M7
0
0
0
1
•
•
0
0
0
64
M6
1
1
1
0
•
•
1
1
1
32
M5
1
1
1
0
•
•
0
0
0
16
M4
1
1
1
0
•
•
1
1
1
8
M3
1
1
1
0
•
•
1
1
1
4
M2
1
1
1
0
•
•
1
1
1
2
M1
0
1
1
0
•
•
0
0
1
1
M0
1
0
1
0
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of 16MHz.
IDT™ / ICS™
3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
4
ICS84314AY-02 REV. A MARCH 24, 2009
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Table 3C. Programmable Output Divider Function Table (Serial Programming Mode Only)
Inputs
N1 Logic
0
0
1
1
N0 Logic
0
1
0
1
N Divide
1
2
4
8
Minimum
250
125
62.5
31.25
Outputs
Q[0:3], nQ[0:3]
Maximum
700
350
175
87.5
Table 3D. N Output Divider Function Table (Serial Load)
N1 Logic Value
0
0
1
1
N0 Logic Value
0
1
0
1
N Output Divide
÷1
÷2 (Power-up Default)
÷4
÷8
Table 3E. SSC Function Table
SSC
0
1
SSC State
Off (Power-up Default)
Enabled
Table 3F. XTAL_SEL Function Table
XTAL_SEL
0
1 (default)
Operation
Selects TEST_CLK as reference frequency input.
Selects the crystal interface (XTAL_IN, XTAL_OUT) as reference frequency input.
Table 3G. VCO_SEL Function Table
VCO_SEL
0
1 (default)
Operation
Reference input signal bypasses the PLL. AC specifications do not apply in PLL bypass mode.
The reference input signal is frequency-divided by the output divider
PLL mode (clock synthesis).
IDT™ / ICS™
3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER
5
ICS84314AY-02 REV. A MARCH 24, 2009
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