Low Skew, 1-to-4, Crystal-to-LVCMOS/
LVTTL Fanout Buffer
Data Sheet
83904-02
G
ENERAL
D
ESCRIPTION
The 83904-02 is a low skew, high performance 1-to-4 Crystal-to-
LVCMOS Fanout Buffer. The 83904-02 has selectable single-ended
clock or two crystal-oscillator inputs. There is an output enable to
disable the outputs by placing them into a high-impedance state.
Guaranteed output and par t-to-par t skew characteristics
make the 83904-02 ideal for those applications demand-
ing well defined performance and repeatability.
F
EATURES
•
Four LVCMOS/LVTTL outputs,
19Ω typical output impedance
@ V
DD
= V
DDO
= 3.3V
•
Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
•
Crystal input frequencry range: 12MHz – 38.88MHz
•
Output frequency: 200MHz (maximum)
•
Output Skew: 40ps (maximum)
@ V
DD
= V
DDO
= 3.3V
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz – 1MHz): 0.16ps (typical) @ V
DD
= V
DDO
= 3.3V
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz ..............-118.4 dBc/Hz
1kHz ..............-141.5 dBc/Hz
10kHz ..............-157.2 dBc/Hz
100kHz ..............-157.2 dBc/Hz
•
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
B
LOCK
D
IAGRAM
OE
CLK_SEL0
CLK_SEL1
Pullup
Pulldown
Pulldown
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
XTAL_IN0
P
IN
A
SSIGNMENT
OSC
0 0
Q0
CLK_SEL0
XTAL_OUT0
XTAL_IN0
V
DD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DDO
Q0
Q1
GND
Q2
Q3
V
DDO
OE
XTAL_OUT0
Q1
XTAL_IN1
OSC
0 1
Q2
XTAL_OUT1
83904-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
CLK Pulldown
1 0
1 1
Q3
©2016 Integrated Device Technology, Inc
1
Revision A March 17, 2016
83904-02 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 3
4
5, 6
8
9
10, 16
11, 12, 14, 15
13
Name
CLK_SEL0,
CLK_SEL1
XTAL_OUT0,
XTAL_IN0
V
DD
XTAL_IN1,
XTAL_OUT1
CLK
OE
V
DDO
Q3, Q2, Q1, Q0
GND
Input
Input
Power
Input
Input
Input
Power
Output
Power
Type
Pulldown
Description
Clock select inputs. See Table 3, Input Reference Function Table.
LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Positive supply pin.
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2.0V
V
DDO
= 3.3V
R
OUT
Output Impedance
V
DDO
= 2.5V
V
DDO
= 1.8V
Test Conditions
Minimum
Typical
4
51
51
8
7
7
19
21
32
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. I
NPUT
R
EFERENCE
F
UNCTION
T
ABLE
Control Inputs
CLK_SEL1
CLK_SEL0
0
0
0
1
1
1
0
1
Reference
XTAL0 (default)
XTAL1
CLK
CLK
©2016 Integrated Device Technology, Inc
2
Revision A March 17, 2016
83904-02 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
100.3°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load & XTALx selected @ 12MHz
No Load & CLK selected
No Load & CLK selected
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
7
1
1
Units
V
V
mA
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load & XTALx selected @ 12MHz
No Load & CLK selected
No Load & CLK selected
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
7
1
1
Units
V
V
mA
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load & XTALx selected @ 12MHz
No Load & CLK selected
No Load & CLK selected
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
7
1
1
Units
V
V
mA
mA
mA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load & XTALx selected @ 12MHz
No Load & CLK selected
No Load & CLK selected
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
3
1
1
Units
V
V
mA
mA
mA
©2016 Integrated Device Technology, Inc
3
Revision A March 17, 2016
83904-02 Data Sheet
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load & XTALx selected @ 12MHz
No Load & CLK selected
No Load & CLK selected
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
3
1
1
Units
V
V
mA
mA
mA
T
ABLE
4F. DC C
HARACTERISTICS
,
T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK, CLK_
SEL0:1
OE
I
IL
Input Low Current
CLK, CLK_
SEL0:1
OE
V
OH
Output HighVoltage
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%; NOTE 1
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
-5
-150
2.6
1.8
1.2
0.6
0.5
0.4
Minimum
2.2
1.6
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.9
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
Input High Current
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement section, “Load Test Circuit” diagrams.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
12
Test Conditions
Minimum
Typical Maximum
38.88
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
©2016 Integrated Device Technology, Inc
4
Revision A March 17, 2016
83904-02 Data Sheet
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
tp
LH
tsk(o)
tsk(pp)
tjit(Ø)
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
w/external XTAL
w/external CLK
1.4
1.9
Test Conditions
Minimum
12
Typical
Maximum
38.88
200
2.4
40
700
25MHz, Integration Range:
100Hz – 1MHz
20% to 80%
ƒ < 150MHz
100
45
46
0.16
800
55
54
10
10
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
Propagation Delay, Low-to-High; NOTE
1
Output Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output
Duty Cycle
w/external XTAL
w/external CLK
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
tp
LH
tsk(o)
tsk(pp)
tjit(Ø)
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
w/external XTAL
w/external CLK
1.5
2.0
Test Conditions
Minimum
12
Typical
Maximum
38.88
200
2.5
40
700
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
ƒ < 150MHz
100
45
46
0.16
800
55
54
10
10
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
Propagation Delay, Low-to-High; NOTE
1
Output Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output
Duty Cycle
w/external XTAL
w/external CLK
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
5
Revision A March 17, 2016
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