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IDT70T3519S166BFI

Description
Multi-Port SRAM, 256KX36, 12ns, CMOS, PBGA208
Categorystorage    storage   
File Size427KB,28 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

IDT70T3519S166BFI Overview

Multi-Port SRAM, 256KX36, 12ns, CMOS, PBGA208

IDT70T3519S166BFI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
package instructionFBGA, BGA208,17X17,32
Reach Compliance Codenot_compliant
Maximum access time12 ns
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B208
JESD-609 codee0
memory density9437184 bit
Memory IC TypeMULTI-PORT SRAM
memory width36
Humidity sensitivity level3
Number of ports2
Number of terminals208
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeFBGA
Encapsulate equivalent codeBGA208,17X17,32
Package shapeSQUARE
Package formGRID ARRAY, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5,2.5/3.3 V
Certification statusNot Qualified
Maximum standby current0.015 A
Minimum standby current2.4 V
Maximum slew rate0.51 mA
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
Features:
HIGH-SPEED 2.5V
256/128/64K x 36
IDT70T3519/99/89S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG is not supported on the 208-
pin PQFP package
BE
3R
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
BE
3L
Functional Block Diagram
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
R/W
R
CE
0L
CE
1L
1
0
1/0
B B
WW
0 1
L L
B B B B
WWW W
2 3 3 2
L L R R
B B
WW
1 0
R R
1
0
1/0
CE
0R
CE
1R
OE
L
OE
R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
D out18-26_R
D out27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
0a 1a 0b 1b 0c 1c 0d 1d
0/1
,
FT/PIPE
R
FT/PIPE
L
0/1
a bc d
dcb a
256/128/64K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
17L
(1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
A
17R(1)
CLK
R
,
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
TCK
TMS
TRST
CE
0 L
CE1 L
R /
W
L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0 R
CE1 R
R/
W
R
JTAG
TDO
COL
R
INT
R
COL
L
INT
L
ZZ
L
(2)
NOTES:
1. Address A
17
is a NC for the IDT70T3599. Also, Addresses A
17
and A
16
are NC's for the IDT70T3589.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
ZZ
CONTROL
LOGIC
ZZ
R
(2)
5666 drw 01
APRIL 2004
DSC 5666/6
1
©2004 Integrated Device Technology, Inc.

IDT70T3519S166BFI Related Products

IDT70T3519S166BFI IDT70T3599S166BFI IDT70T3589S166BFI IDT70T3599S166DRI
Description Multi-Port SRAM, 256KX36, 12ns, CMOS, PBGA208 Multi-Port SRAM, 128KX36, 12ns, CMOS, PBGA208 Multi-Port SRAM, 64KX36, 12ns, CMOS, PBGA208 Dual-Port SRAM, 128KX36, 12ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208
Is it lead-free? Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Reach Compliance Code not_compliant not_compliant not_compliant not_compliant
Maximum access time 12 ns 12 ns 12 ns 12 ns
Maximum clock frequency (fCLK) 166 MHz 166 MHz 166 MHz 166 MHz
I/O type COMMON COMMON COMMON COMMON
JESD-30 code S-PBGA-B208 S-PBGA-B208 S-PBGA-B208 S-PQFP-G208
JESD-609 code e0 e0 e0 e0
memory density 9437184 bit 4718592 bit 2359296 bit 4718592 bit
Memory IC Type MULTI-PORT SRAM MULTI-PORT SRAM MULTI-PORT SRAM DUAL-PORT SRAM
memory width 36 36 36 36
Humidity sensitivity level 3 3 3 3
Number of ports 2 2 2 2
Number of terminals 208 208 208 208
word count 262144 words 131072 words 65536 words 131072 words
character code 256000 128000 64000 128000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
organize 256KX36 128KX36 64KX36 128KX36
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code FBGA FBGA FBGA FQFP
Encapsulate equivalent code BGA208,17X17,32 BGA208,17X17,32 BGA208,17X17,32 QFP208,1.2SQ,20
Package shape SQUARE SQUARE SQUARE SQUARE
Package form GRID ARRAY, FINE PITCH GRID ARRAY, FINE PITCH GRID ARRAY, FINE PITCH FLATPACK, FINE PITCH
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 225 225 225 225
power supply 2.5,2.5/3.3 V 2.5,2.5/3.3 V 2.5,2.5/3.3 V 2.5,2.5/3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum standby current 0.015 A 0.02 A 0.02 A 0.02 A
Minimum standby current 2.4 V 2.4 V 2.4 V 2.4 V
Maximum slew rate 0.51 mA 0.51 mA 0.51 mA 0.51 mA
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn/Pb)
Terminal form BALL BALL BALL GULL WING
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.5 mm
Terminal location BOTTOM BOTTOM BOTTOM QUAD
Maximum time at peak reflow temperature 20 20 20 20
package instruction FBGA, BGA208,17X17,32 FBGA, BGA208,17X17,32 - FQFP, QFP208,1.2SQ,20
Base Number Matches - 1 1 1
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