KM48V8000B, KM48V8100B
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-
thermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- KM48V8000B/B-L(3.3V, 8K Ref.)
- KM48V8100B/B-L(3.3V, 4K Ref.)
•
Active Power Dissipation
Unit : mW
Speed
-45
-5
-6
•
Refresh Cycles
Part
NO.
KM48V8000B*
KM48V8100B
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
CAS
W
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
4K
468
432
396
8K
360
324
288
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
VBB Generator
Refresh Control
Refresh Counter
Memory Array
8,388,608 x 8
Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
•
Performance Range
Speed
-45
-5
-6
Refresh Timer
Row Decoder
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
80ns
90ns
110ns
t
PC
31ns
35ns
40ns
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
KM48V8000B, KM48V8100B
CMOS DRAM
PIN CONFIGURATION
(Top Views)
•KM48V80(1)00BK
•KM48V80(1)00BS
V
CC
DQ0
DQ1
DQ2
DQ3
N.C
V
CC
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
N.C
V
CC
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
(K : 400mil SOJ)
(S : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name
A0 - A12
A0 - A11
DQ0 - 7
V
SS
RAS
CAS
W
OE
V
CC
N.C
Pin Function
Address Inputs(8K Product)
Address Inputs(4K Product)
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+3.3V)
No Connection
KM48V8000B, KM48V8100B
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN,
V
OUT
V
CC
Tstg
P
D
I
OS
Rating
-0.5 to +6.5
-0.5 to +4.6
-55 to +150
1
50
CMOS DRAM
Units
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
*2
Typ
3.3
0
-
-
Max
3.6
0
+5.5
*1
0.8
Units
V
V
V
V
*1 : 6.5V at pulse width≤15ns which is measured at V
CC
*2 : -1.3 at pulse width≤15ns which is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
CC
+0.3V,
all other pins not under test=0 Volt)
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-2mA)
Output Low Voltage Level(I
OL
=2mA)
Symbol
I
I(L)
I
O(L)
V
OH
V
OL
Min
-5
-5
2.4
-
Max
5
5
-
0.4
Units
uA
uA
V
V
KM48V8000B, KM48V8100B
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
Power
Speed
-45
-5
-6
Don′t care
-45
-5
-6
-45
-5
-6
Don′t care
-45
-5
-6
Don′t care
Don′t care
Max
KM48V8000B
100
90
80
2
2
100
90
80
70
60
50
500
300
100
90
80
400
400
KM48V8100B
130
120
110
2
2
130
120
110
80
70
60
500
300
130
120
110
400
400
CMOS DRAM
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
mA
mA
mA
uA
uA
I
CC1
Don′t care
Normal
L
Don′t care
I
CC2
I
CC3
I
CC4
Don′t care
Normal
L
Don′t care
L
L
I
CC5
I
CC6
I
CC7
I
CCS
I
CC1
* : Operating Current (RAS and CAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Fast Page Mode Current (RAS=V
IL
, CAS, Address cycling @
t
PC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @
t
RC
=min)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=CAS-before-RAS cycling or 0.2V,
W, OE=V
IH
, Address=Don′t care DQ=Open, T
RC
=31.25us
I
CCS
: Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=V
CC
-0.2V or 0.2V, DQ0 ~ DQ7=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time,
t
PC
.
KM48V8000B, KM48V8100B
CAPACITANCE
(T
A
=25°C, V
CC
=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ7]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 1,2)
Test condition : V
CC
=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Symbol
Min
-45
Max
Min
90
133
45
12
23
0
0
1
25
45
12
45
12
18
13
5
0
8
0
8
23
0
0
0
8
8
13
12
0
10
10K
33
22
10K
13
50
0
0
1
30
50
13
50
13
20
15
5
0
10
0
10
25
0
0
0
10
10
15
13
0
10
10K
37
25
10K
13
50
50
13
25
0
0
1
40
60
15
60
15
20
15
5
0
10
0
10
30
0
0
0
10
10
15
15
0
10
10K
45
30
10K
13
50
-5
Max
Min
110
153
60
15
30
-6
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
9
8
8
4
10
3,4,10
3,4,5
3,10
3
6
2
Units
Note
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
80
115
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