K4M28323LH - F(H)N/G/L/F
1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
•
•
•
•
•
Auto refresh.
64ms refresh period (4K cycle).
Commercial Temperature Operation (-25°C ~ 70°C).
Extended Temperature Operation (-25°C ~ 85°C).
90Balls FBGA ( -FXXX -Pb, -HXXX -Pb Free).
Mobile SDRAM
GENERAL DESCRIPTION
The K4M28323LH is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4M28323LH-F(H)N/G/L/F60
K4M28323LH-F(H)N/G/L/F75
K4M28323LH-F(H)N/G/L/F7L
Max Freq.
166MHz(CL=3)
133MHz(CL=3), 111MHz(CL=2)
133MHz(CL=3)
*1
, 83MHz(CL=2)
LVCMOS
90 FBGA Pb
(Pb Free)
Interface
Package
- F(H)N/G : Low Power, Extended Temperature(-25°C ~ 85°C)
- F(H)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C)
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
Organization
4M x 32
Bank
BA0, BA1
Row
A0 - A11
Column Address
A0 - A7
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
1
January 2006
K4M28323LH - F(H)N/G/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.0
50
Mobile SDRAM
Unit
V
V
°C
W
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial)
Parameter
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
V
IH
V
IL
V
OH
V
OL
I
LI
2.3
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-2
2.5
2.5
0
-
-
-
2.7
V
DDQ
+ 0.3
0.3
-
0.2
2
V
V
V
V
V
uA
1
2
3
I
OH
= -0.1mA
I
OL
= 0.1mA
4
Symbol
V
DD
Min
2.3
Typ
2.5
Max
2.7
Unit
V
Note
1
NOTES :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VIH (max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
4. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
31
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
1.5
1.5
1.5
2.0
Max
3.5
3.0
3.0
4.5
Unit
pF
pF
pF
pF
Note
4
January 2006
K4M28323LH - F(H)N/G/L/F
DC CHARACTERISTICS
Mobile SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Symbol
Test Condition
-60
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
-75
-7L
Unit
Note
I
CC1
80
65
65
mA
1
I
CC2
P
0.5
mA
0.5
12
mA
5
5
mA
2
25
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
I
CC3
P
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-N/L
Internal TCSR
45
*4
200
150
130
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
15
mA
Operating Current
(Burst Mode)
I
CC
4
100
75
65
mA
1
Refresh Current
I
CC
5
140
130
330
120
mA
uA
2
85/70
330
230
190
°C
3
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-G/F
Full Array
1/2 of Full Array
1/4 of Full Array
uA
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In comercial Temp : 45°C/Max 70°C. In extended Temp : 45°C/Max 85°C.
4. It has +/-5
°C
tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
5
January 2006
FPGA/CPLD
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