CY7C346B-35JIT datasheet, PDF - EEWORLD Datasheet

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CY7C346B-35JIT: DescriptionOT PLD, 55ns, CMOS, PQCC84, PLASTIC, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size430KB，15 Pages; ManufacturerCypress Semiconductor

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CY7C346B-35JIT Overview

OT PLD, 55ns, CMOS, PQCC84, PLASTIC, LCC-84

CY7C346B-35JIT Parametric

Parameter Name	Attribute value
Maker	Cypress Semiconductor
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	84
Reach Compliance Code	unknown
Other features	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency	40 MHz
JESD-30 code	S-PQCC-J84
length	29.3116 mm
Dedicated input times	19
Number of I/O lines	48
Number of terminals	84
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	19 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	OT PLD
propagation delay	55 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	29.3116 mm

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USE ULTRA37000™ FOR

ALL NEW DESIGNS

CY7C346B

128-Macrocell MAX

EPLD

Features

• 128 macrocells in eight logic array blocks (LABs)

• 20 dedicated inputs, up to 64 bidirectional I/O pins

• Programmable interconnect array

• Advanced 0.65-micron CMOS technology to increase

performance

• Available in 84-pin CLCC, PLCC, and 100-pin PGA,

PQFP

The 128 macrocells in the CY7C346B are divided into eight

LABs, 16 per LAB. There are 256 expander product terms, 32

per LAB, to be used and shared by the macrocells within each

LAB.

Each LAB is interconnected through the programmable inter-

connect array, allowing all signals to be routed throughout the

chip.

The speed and density of the CY7C346B allow it to be used in

a wide range of applications, from replacement of large

amounts of 7400-series TTL logic, to complex controllers and

multifunction chips. With greater than 25 times the functionality

of 20-pin PLDs, the CY7C346B allows the replacement of over

50 TTL CY7C346B. By replacing large amounts of logic, the

CY7C346B reduces board space, part count, and increases

system reliability.

Functional Description

The CY7C346B is an Erasable Programmable Logic Device

(EPLD) in which CMOS EPROM cells are used to configure

logic functions within the device. The MAX

architecture is

100% user-configurable, allowing the device to accommodate

a variety of independent logic functions.

Logic Block Diagram

. 1 (C7) [16]

. 78 (A10) [9]

. 79 (B9) [10]

80 (A9) [11]

. 83 (A8) [14]

. 84 (B7) [15]

. 2 (A7) [17]

. 5 (C6) [20]

. 6 (A5) [21]

. 7 (B5) [22]

. INPUT/CLK

.....

INPUT

.....

INPUT

.....

INPUT

.....

INPUT

.....

INPUT

.....

INPUT

.....

INPUT

.....

INPUT

.....

INPUT

SYSTEM CLOCK

LAB A

MACROCELL

LAB H

MACROCELL 120

MACROCELL 119

MACROCELL 118

MACROCELL 117

MACROCELL 116

MACROCELL 115

MACROCELL 114

MACROCELL 113

MACROCELL 121–128

LAB G

MACROCELL 104

MACROCELL 103

MACROCELL 102

MACROCELL 101

MACROCELL 100

MACROCELL 99

MACROCELL 98

MACROCELL 97

MACROCELL 105–112

LAB F

MACROCELL 88

MACROCELL 87

MACROCELL 86

MACROCELL 85

MACROCELL 84

MACROCELL 83

MACROCELL 82

MACROCELL 81

MACROCELL 86–96

LAB E

MACROCELL

[58]

[57]

[56]

[55]

[54]

[53]

[52]

[51]

(M4) NC

(N3) NC

(M3) 55

(N2) 54

(M2) 53

(N1) 52

(L2) 51

(M1) 50

INPUT [59]

INPUT [60]

INPUT [61]

INPUT [64]

INPUT [65]

INPUT [66]

INPUT [67]

INPUT [70]

INPUT [71]

INPUT [72]

(N4)

(M5)

(N5)

(N6)

(M7)

(L7)

(N7)

(L8)

(N9)

(M9)

8 (B13) [1]

9 (C12) [2]

10 (A13) [3]

11 (B12) [4]

12 (A12) [5]

13 (11) [6]

NC (A11) [7]

NC (B10) [8]

[100] (C13) NC

[99] (D12) NC

[98] (D13) 77

[97] (E12) 76

[96] (E13) 75

[95] (F11) 74

[92] (G13) 73

[91] (G11) 72

MACROCELL 9–16

LAB B

MACROCELL

14 (A4)

15 (B4)

16 (A3)

17 (A2)

18 (B3)

21 (A1)

NC (B2)

NC (B1)

[23]

[24]

[25]

[26]

[27]

[28]

[29]

[30]

[90]

[89]

[86]

[85]

[84]

[83]

[82]

[81]

(G12) NC

(H13) NC

(J13) 71

(J12) 70

(K13) 69

(K12) 68

(L13) 67

(L12) 64

MACROCELL 25–32

LAB C

MACROCELL

22 (C2) [31]

25 (C1) [32]

26 (D2) [33]

27 (D1) [34]

28 (E2) [35]

29 (E1) [36]

NC (F1) [39]

NC (G2) [40]

[80]

[79]

[78]

[77]

[76]

[75]

[74]

[73]

(M13)

(M12)

(N13)

(M11)

(N12)

(N11)

(M10)

(N10)

MACROCELL 41–48

LAB D

30 (G3) [41]

31 (G1) [42]

32 (H3) [45]

33 (J1) [46]

34 (J2) [47]

35 (K1) [48]

NC (K2) [49]

NC (L1) [50]

MACROCELL

MACROCELL 57– 64

3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8)

16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6)

[18, 19, 43, 44, 68, 69, 93, 94]

[12, 13, 37, 38, 62, 63, 87, 88]

VCC

GND

MACROCELL 73– 80

() – PERTAIN TO 100-PIN PGA PACKAGE

[ ] – PERTAIN TO 100-PIN PQFP PACKAGE

Cypress Semiconductor Corporation

Document #: 38-03037 Rev. *C

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised April 9, 2004

CY7C346B-35JIT Related Products

	CY7C346B-35JIT	CY7C346B-35JCT	CY7C346B-25JCT	CY7C346B-25JIT
Description	OT PLD, 55ns, CMOS, PQCC84, PLASTIC, LCC-84	OT PLD, 55ns, CMOS, PQCC84, PLASTIC, LCC-84	OT PLD, 40ns, CMOS, PQCC84, PLASTIC, LCC-84	OT PLD, 40ns, CMOS, PQCC84, PLASTIC, LCC-84
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	LCC	LCC	LCC	LCC
package instruction	QCCJ,	QCCJ,	QCCJ,	QCCJ,
Contacts	84	84	84	84
Reach Compliance Code	unknown	unknown	unknown	unknown
Other features	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency	40 MHz	40 MHz	62.5 MHz	62.5 MHz
JESD-30 code	S-PQCC-J84	S-PQCC-J84	S-PQCC-J84	S-PQCC-J84
length	29.3116 mm	29.3116 mm	29.3116 mm	29.3116 mm
Dedicated input times	19	19	19	19
Number of I/O lines	48	48	48	48
Number of terminals	84	84	84	84
Maximum operating temperature	85 °C	70 °C	70 °C	85 °C
organize	19 DEDICATED INPUTS, 48 I/O	19 DEDICATED INPUTS, 48 I/O	19 DEDICATED INPUTS, 48 I/O	19 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ	QCCJ
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Programmable logic type	OT PLD	OT PLD	OT PLD	OT PLD
propagation delay	55 ns	55 ns	40 ns	40 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm	5.08 mm	5.08 mm
Maximum supply voltage	5.5 V	5.25 V	5.25 V	5.5 V
Minimum supply voltage	4.5 V	4.75 V	4.75 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal form	J BEND	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
width	29.3116 mm	29.3116 mm	29.3116 mm	29.3116 mm

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