PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
PM5363
TUPP+622
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
FOR 622 MBIT/S INTERFACES
DATASHEET
RELEASED
ISSUE 4: JULY 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
REVISION HISTORY
Issue
No.
Issue 4
Issue Date
July 2000
Details of Change
Update for revision B device.
De-document TU3 Inband
Error feature. Added changes
to timing and operating
conditions. All Input Hold
Times for SCLK (19.44MHz)
are changed from 1ns to
1.5ns. All Output Max Prop
Delays for HSCLK
(77.76MHz) changed from
8ns to 9ns. All Output Min
Prop Delay for SCLK
(19.44MHz) changed from
2ns to 3.5ns. Operating
Condition for V
DD3.3
changed
from 3.3V
±
10% to 3.3V
±
0.3V and operating condition
for V
DD2.5
changed from 2.5V
±
10% to 2.5V
±
0.2V.
TUGEN Bit and TUGBYP Bit
description changed. Device
ID Revision Number, SOS Bit
description and Boundary
Scan ID changed.
Update Data-sheet portion to
preliminary.
Update pin and register
description.
Document created.
Issue 3
Issue 2
Issue 1
Nov 1999
May 1999
December
1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
CONTENTS
1
2
3
4
5
FEATURES ............................................................................................1
APPLICATIONS .....................................................................................5
REFERENCES.......................................................................................6
DEFINITIONS ........................................................................................8
APPLICATION EXAMPLES ...................................................................9
5.1
5.2
5.3
5.4
6
7
8
9
10
STS-12 (STM-4) AGGREGATE INTERFACE..............................9
QUAD STS-3 (STM-1) AGGREGATE INTERFACE ..................10
STS-48 (STM-16) AGGREGATE INTERFACE.......................... 11
TUPP-PLUS COMPATIBILITY AND TUPP+622
FEATURE ENHANCEMENTS...................................................12
DESCRIPTION.....................................................................................13
PIN DIAGRAM .....................................................................................15
BLOCK DIAGRAM ...............................................................................16
PIN DESCRIPTION (304) ....................................................................17
FUNCTIONAL DESCRIPTION.............................................................88
10.1
10.2
10.3
INPUT BUS DEMULTIPLEXER ................................................89
OUTPUT BUS MULTIPLEXER..................................................90
TRIBUTARY PAYLOAD PROCESSOR (VTPP).........................91
10.3.1 CLOCK GENERATOR....................................................91
10.3.2 INCOMING TIMING GENERATOR.................................91
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
10.3.3 INCOMING MULTIFRAME DETECTOR.........................92
10.3.4 POINTER INTERPRETER .............................................92
10.3.5 PAYLOAD BUFFER........................................................96
10.3.6 OUTGOING TIMING GENERATOR ...............................96
10.3.7 POINTER GENERATOR ................................................97
10.4
TRIBUTARY PATH OVERHEAD PROCESSOR
(RTOP) ....................................................................................100
10.4.1 CLOCK GENERATOR..................................................101
10.4.2 TIMING GENERATOR .................................................101
10.4.3 ERROR MONITOR.......................................................101
10.4.4 IN-BAND ERROR REPORT .........................................103
10.4.5 EXTRACT.....................................................................104
10.5
TRIBUTARY TRACE BUFFER (RTTB) ...................................104
10.5.1 CLOCK GENERATOR..................................................104
10.5.2 TIMING GENERATOR .................................................105
10.5.3 EXTRACT.....................................................................105
10.5.4 ALARM MONITOR .......................................................105
10.5.5 BUFFER .......................................................................106
10.6
10.7
11
JTAG TEST ACCESS PORT ...................................................106
MICROPROCESSOR INTERFACE ........................................107
NORMAL MODE REGISTER DESCRIPTION ................................... 117
11.1
TOP LEVEL CONFIGURATION REGISTERS......................... 118
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PM5363 TUPP+622
TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
11.2
11.3
11.4
12
VTPP #1, VTPP #2 AND VTPP #3 REGISTERS ....................169
RTOP #1, RTOP #2 AND RTOP #3 REGISTERS ...................205
RTTB #1, RTTB #2 AND RTTB #3 REGISTERS.....................298
TEST FEATURES DESCRIPTION.....................................................325
12.1
12.2
I/O TEST MODE......................................................................332
JTAG TEST PORT ..................................................................364
13
OPERATION ......................................................................................376
13.1
13.2
13.3
13.4
13.5
13.6
13.7
CONFIGURATION OPTIONS .................................................376
STS-1 MODE ..........................................................................378
AU3 MODE..............................................................................378
AU4 MODE..............................................................................379
BYPASS OPTIONS .................................................................381
POWER SEQUENCING..........................................................382
JTAG SUPPORT .....................................................................382
13.7.1 TAP CONTROLLER .....................................................384
13.7.2 BOUNDARY SCAN INSTRUCTIONS...........................387
14
15
16
17
18
FUNCTIONAL TIMING.......................................................................389
ABSOLUTE MAXIMUM RATINGS .....................................................408
D.C. CHARACTERISTICS .................................................................409
MICROPROCESSOR INTERFACE TIMING
CHARACTERISTICS .........................................................................412
TUPP+622 TIMING CHARACTERISTICS .........................................420
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii