MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document from Analog Marketing: MC33701/D
Rev 1.0, 05/2003
Preliminary Information
1.5 A Switch-Mode Power Supply
with Linear Regulator
The 33701 provides the means to efficiently supply the Power QUICC™ I,
II, and other families of Motorola microprocessors and DSPs. The 33701
incorporates a high-performance switching regulator, providing the direct
supply for the microprocessor’s core, and a low dropout (LDO) linear regulator
control circuit providing the microprocessor I/O and bus voltage.
The switching regulator is a high-efficiency synchronous buck regulator with
integrated 50 mΩ N-channel power MOSFETs to provide protection features
and to allow space-efficient, compact design.
The 33701 incorporates many advanced features; e.g., precisely
maintained up/down power sequencing, ensuring the proper operation and
protection of the CPU and power system.
Features
• Operating Voltage: 2.8 V to 6.0 V
• High-Accuracy Output Voltages
• Fast Transient Response
• Switcher Output Current Up to 1.5 A
• Undervoltage Lockout
• Power Sequencing
• Programmable Watchdog Timer
•
•
•
•
Voltage Margining via
Bus
Overcurrent Protection
Reset with Programmable Power-ON Delay
Enable Inputs
I
2
C™
33701
POWER SUPPLY
INTEGRATED CIRCUIT
DWB SUFFIX
CASE 1324-02
32-LEAD SOICW
ORDERING INFORMATION
Device
PC33701DWB/R2
Temperature
Range (T
A
)
-40 to 85°C
Package
32 SOICW
I
2
C is a trademark of Phillips Corporation.
33701 Simplified Application Diagram
2.8
V
V to
3. 5 V
V
put
2.8 to 1
6.0
In
MC3 3703
33701
V
IN2
VIN2
V
IN1
VIN1
O the r
Circuits
LDRV
CS
LDO
LFB
V
BD
VBD
V
BST
VBST
SR
RT
ADDR
SDA
SCL
GND
EN1
EN2
V
LDO
=
0.8 t o 5. 0 V
(Adjustable)
VDDH (I/Os)
MPC8XXX
MPC85xx
PORESET
RES ET
BO OT
SW
VBS T
V
OUT
=
0.8 to 5.0 V
(Adjus table)
VDDL (Core)
V
OUT
CLKS YN VOUT
CLKS EL PG ND
Optional
FREQ
I NV
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2003
V
IN1
VIN1
VIN
V
IN
V
DDI
VDDI
Internal
Supply
V
BST
VBST
V
DDI
VDDI
V
DDI
VDDI
V
BST
VBST
8.0V
V
BST
VBST
V
BD
VBD
Boost
Control
Vref
Vref
EN1
EN2
RESET
Reset
Control
RT
POR
Timer
Reset
Power
Sequencing
Voltage Margining
W-dog Timer
Watchdog Timer
SysCon
INV
LFB
I
2
C
Control
SysCon
Thermal
Limit
SoftSt
I
2
C
Control
ADDR
SDA
SCL
I
2
C
Interface
Switcher
Oscillator
300kHz
CLKSEL
CLKSYN
Figure 1. 33701 Simplified Block Diagram
33701
2
+
Vref
Power
Enable
V
DDI
VDDI
V
DDI
VDDI
LDRV
CS
LDO
-
-
-
FREQ
Bandgap
Voltage
Reference
V
DDI
VDDI
Linear
Regulator
Control
I
LIM
I-lim
Vref
LFB
V
LDO
Pow. Seq.
VLDO
PWR Seq.
Power
Down
UVLO
V
OUT
VOUT
V
BST
VBST
Q4
V
BST
VBST
LCMP
BOOT
V
IN2
VIN2
Current
Limit
V
DDI
VDDI
(2)
Buck
HS
&
LS
Driver
Q1
SW
Q2
(2)
PGND
Buck
Control
Logic
PWM
Comp.
+
-
Slope
Comp.
Error
Amp.
To Reset
0.8V Control
+
-
V
OUT
VOUT
(2)
INV
Pow.
PWR Seq.
Seq.
PGND
(4)
Q3
V
OUT
VOUT
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
FREQ
INV
V
OUT
V
IN2
V
IN2
SW
SW
GND
GND
PGND
PGND
V
BD
V
BST
BOOT
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CLKSYN
CLKSEL
RESET
RT
EN2
EN1
ADDR
GND
GND
V
DD1
V
IN1
LDRV
CS
LDO
LFB
LCMP
PIN FUNCTION DESCRIPTION
Pin
1
Pin Name
FREQ
Formal Name
Oscillator Frequency
Definition
This selection switcher pin can be adjusted by connecting external resistor R
F
to the
FREQ pin. The default switching frequency (FREQ pin left open or tied to V
DDI
) is set
to 300 kHz.
Buck Controller Error Amplifier inverting input.
Output voltage of the buck converter. Input pin of the switching regulator power
sequence control circuit.
Buck regulator power input. Drain of the high-side power MOSFET.
Buck regulator switching node. This pin is connected to the inductor.
Analog ground of the IC, thermal heatsinking.
Buck regulator power ground.
Drain of the internal boost regulator power MOSFET.
Internal boost regulator output voltage. The internal boost regulator provides a 20 mA
output current to supply the drive circuits for the integrated power MOSFETs and the
external N-channel power MOSFET of the linear regulator. The voltage at the V
BST
pin
is 8.0 V nominal.
Bootstrap capacitor input.
I
2
C bus pin. Serial data.
I
2
C bus pin. Serial clock.
Linear regulator compensation pin.
Linear regulator feedback pin.
Input pin of the linear regulator power sequence control circuit.
Current sense pin of the LDO. Overcurrent protection of the linear regulator external
power MOSFET. The voltage drop over the LDO current sense resistor R
S
is sensed
between the CS and LDO pins. The LDO current limit can be adjusted by selecting the
proper value of the current sensing resistor R
S
.
LDO gate drive of the external pass N-channel MOSFET.
The input supply pin for the integrated circuit. The internal circuits of the IC are supplied
through this pin.
2
3
4, 5
6, 7
8, 9
24, 25
10, 11
12
13
INV
V
OUT
V
IN2
SW
Inverting Input
Output Voltage
Input Voltage 2
Switch
Ground
Power Ground
Boost Drain
Boost Voltage
GND
PGND
V
BD
V
BST
14
15
16
17
18
19
20
BOOT
SDA
Bootstrap
Serial Data
Serial Clock
Linear Compensation
Linear Feedback
Linear Regulator
Current Sense
SCL
LCMP
LFB
LDO
CS
21
22
LDRV
V
IN1
Linear Drive
Input Voltage 1
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33701
3
PIN FUNCTION DESCRIPTION (continued)
Pin
23
26
Pin Name
V
DDI
ADDR
Formal Name
Power Supply
Address
Internal supply voltage.
I
2
C address selection. This pin can be either left open, tied to V
DDI
, or grounded through
a 10 kΩ resistor.
Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs
determine operation mode and type of power sequencing of the IC.
Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs
determine operation mode and type of power sequencing of the IC.
This pin allows programming the Power-ON Reset delay by means of an external RC
network.
The Reset Control circuit monitors both the switching regulator and the LDO feedback
voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
This pin sets the CLKSYN pin either as an oscillator output or synchronization input pin.
The CLKSEL pin is also used for the I
2
C address selection.
32
CLKSYN
Clock Synchronization
Oscillator output/synchronization input pin.
Definition
27
28
29
30
EN1
EN2
RT
RESET
Enable 1
Enable 2
Reset Timer
Reset Overbar
31
CLKSEL
Clock Selection
33701
4
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Supply Voltage
Switching Node
Buck Regulator Bootstrap Input (BOOT - SW)
Boost Regulator Output
Boost Regulator Drain
RESET
Drain Voltage
Symbol
V
IN1
, V
IN2
SW
BOOT
V
BST
V
BD
RESET
–
–
–
–
–
Value
-0.3 to 7.0
-1.0 to 7.0
-0.3 to 8.5
-0.3 to 8.5
-0.3 to 9.5
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 8.5
-0.3 to 3.6
Unit
V
V
V
V
V
V
V
V
V
V
V
V
Enable Pins (EN1, EN2)
Logic Pins (SDA, SCL, CLKSYN)
Analog Pins (INV, V
OUT
,
RESET
)
Analog Pins (LDRV
,
LFB, LDO, LCMP, CS)
Analog Pins (CLKSEL, ADDR, RT, FREQ, V
DDI
)
ESD Voltage
Human Body Model
(Note 1)
Machine Model
(Note 2)
Storage Temperature
Power Dissipation (T
A
= 85°C)
(Note 3)
Lead Soldering Temperature
(Note 4)
Maximum Junction Temperature
Thermal Resistance, Junction to Ambient
(Note 5)
Thermal Resistance, Junction to Base
(Note 6)
V
ESD1
V
ESD2
T
STG
P
D
T
SOLDER
T
JMAX
R
θ
JA
R
θ
JB
±2000
±200
-65 to 150
TBD
260
125
68
18
°C
W
°C
°C
°C/W
°C/W
OPERATING CONDITIONS
Supply Voltage (V
IN1
, V
IN2
)
Operational Package Temperature (Ambient Temperature)
V
IN1
, V
IN2
T
A
2.8 to 6.0
-40 to 85
V
°C
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
=100 pF, R
ZAP
=1500
Ω).
2.
3.
4.
5.
6.
ESD2 testing is performed in accordance with the Machine Model (C
ZAP
=200 pF, R
ZAP
=0
Ω).
Maximum power dissipation at indicated junction temperature.
Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/
temperature limits.
Thermal resistance measured in accordance with EIA/JESD51-2.
Theoretical thermal resistance from the die junction to the exposed pins.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33701
5
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