Super Sequencer™ with Margining Control
and Auxiliary ADC Inputs
ADM1066
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
better than 1% accuracy
5 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1–4
5 dual-function inputs, VX1–5:
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers (PDO1–10):
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1–6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs:
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow
voltage adjustment via dc/dc converter trim/feedback
node
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input, REFIN, has 2 input options:
Driven directly from 2.048V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VP1–4, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead 6 mm × 6 mm LFCSP and
48-lead 7 mm × 7 mm TQFP packages
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN
REFOUT REFGND
SDA SCL A1
A0
ADM1066
MUX
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
EEPROM
CLOSED-LOOP
MARGINING SYSTEM
VX1
VX2
VX3
VX4
VX5
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
VP1
VP2
VP3
VP4
VH
AGND
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
VDD
ARBITRATOR
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
GND
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1066 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1066 integrates a 12-bit ADC and six 8-bit
voltage output DACs. These circuits can be used to implement a
closed-loop margining system, which enables supply adjustment
by altering either the feedback node or reference of a dc/dc
converter using the DAC outputs.
(continued on Page 3)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
04609-001
ADM1066
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
Pin Configurations and Function Descriptions ........................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution.................................................................................. 8
Typical Performance Characteristics ............................................. 9
Powering the ADM1066 ................................................................ 12
Inputs................................................................................................ 13
Supply Supervision..................................................................... 13
Programming the Supply Fault Detectors............................... 13
Input Comparator Hysteresis.................................................... 14
Input Glitch Filtering ................................................................. 14
Supply Supervision with VXn Inputs....................................... 14
VXn Pins as Digital Inputs........................................................ 15
Outputs ............................................................................................ 16
Supply Sequencing through Configurable Output Drivers .. 16
Sequencing Engine ......................................................................... 17
Overview...................................................................................... 17
Warnings...................................................................................... 17
SMBus Jump/Unconditional Jump .......................................... 17
Sequencing Engine Application Example ............................... 18
Sequence Detector...................................................................... 19
Monitoring Fault Detector ........................................................ 19
Timeout Detector ....................................................................... 19
Fault Reporting........................................................................... 19
Voltage Readback............................................................................ 20
Supply Supervision with the ADC ........................................... 20
Supply Margining ........................................................................... 21
Overview ..................................................................................... 21
Open-Loop Margining .............................................................. 21
Closed-Loop Supply Margining ............................................... 21
Writing to the DACs .................................................................. 22
Choosing the Size of the Attenuation Resistor....................... 22
DAC Limiting/Other Safety Features ...................................... 22
Applications Diagram .................................................................... 23
Communicating with the ADM1066 ........................................... 24
Configuration Download at Power-Up................................... 24
Updating the Configuration ..................................................... 24
Updating the Sequencing Engine............................................. 25
Internal Registers........................................................................ 25
EEPROM ..................................................................................... 25
Serial Bus Interface..................................................................... 25
Write Operations ........................................................................ 27
Read Operations......................................................................... 29
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADM1066
GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining loop can be used for in-
circuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies),
or can be used dynamically to accurately control the output
voltage of a dc/dc converter.
The device also provides up to ten programmable inputs for
monitoring under, over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs can be used as
logic enables. Six of them can also provide up to a 12 V output
for driving the gate of an N-channel FET, which can be placed
in the path of a supply.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.
AUX2 AUX1
REFIN REFOUT REFGND SDA SCL A1
A0
ADM1066
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
OSC
DEVICE
CONTROLLER
EEPROM
GPI SIGNAL
CONDITIONING
VX1
VX2
VX3
VX4
GPI SIGNAL
CONDITIONING
VX5
SEQUENCING
ENGINE
SFD
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
O/P DRIVER
(HV)
PDO1
PDO2
PDO3
PDO4
PDO5
CONFIGURABLE
O/P DRIVER
(HV)
PDO6
VP1
VP2
VP3
VP4
VH
SFD
CONFIGURABLE
O/P DRIVER
(LV)
PDO7
PDO8
PDO9
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
O/P DRIVER
(LV)
PDO10
PDOGND
SFDGND
VDDCAP
VDD
ARBITRATOR
REG 5.25V
CHARGE PUMP
V
OUT
DAC
V
OUT
DAC
GND
VCCP
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
Figure 2. Detailed Block Diagram
Rev. 0 | Page 3 of 32
04609-002
ADM1066
SPECIFICATIONS
VH = 3.0 V to 14.4 V
1
, VPn = 3.0 V to 6.0 V
1
, T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPn
VP
VH
VDDCAP
C
VDDCAP
POWER SUPPLY
Supply Current, I
VH
, I
VPn
Additional Currents
All PDO FET Drivers On
Current Available from VDDCAP
DACs Supply Current
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPn Pins
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VX Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
ANALOG-TO-DIGITAL CONVERTER
Signal Range
2.2
1
10
Min
3.0
6.0
14.4
5.4
Typ
Max
Unit
V
V
V
V
µF
mA
mA
2
mA
mA
mA
mA
Test Conditions/Comments
Minimum supply required on one of VPn, VH
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1–10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1-6 loaded with 1 µA each,
PDO7–10 off
Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP
6 DACs on with 100 µA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
2.7
10
4.75
4.2
1
6
±0.05
6
2.5
±0.05
2.5
1.25
0.573
1
0.573
1.375
±1
8
0
100
0
V
REFIN
6
3
1.375
14.4
6
%
V
V
%
V
V
V
MΩ
V
%
Bits
µs
µs
V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset
error + input attenuation error
Minimum programmable filter length
Maximum programmable filter length
The ADC can convert signals presented to the VH,
VPn, and VX_GPIn pins. VPn and VH input signals
are attenuated depending on selected range. A
signal at the pin corresponding to the selected
range is from 0.573 V to 1.375 V at the ADC input.
Input Reference Voltage on REFIN Pin,
V
REFIN
Resolution
INL
Gain Error
2.048
12
±2.5
±0.05
V
Bits
LSB
%
Endpoint corrected, V
REFIN
= 2.048 V
V
REFIN
= 2.048 V
Rev. 0 | Page 4 of 32
ADM1066
Parameter
Conversion Time
Offset Error
Input Noise
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Load Regulation
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
PSRR
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
Load Regulation
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
V
OH
I
OUTAVG
Standard (Digital Output) Mode (PDO1–10)
V
OH
0.592
0.796
0.996
1.246
Min
Typ
0.44
84
0.25
8
Max
Unit
ms
ms
LSB
LSB
rms
Bits
6 DACs are individually selectable for centering on
one of four output voltage ranges
0.6
0.8
1
1.25
601.25
2.36
0.603
0.803
1.003
1.253
V
V
V
V
mV
mV
LSB
LSB
%
mV
mV
pF
µs
mV
dB
dB
V
mV
mV
µF
mV
dB
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, 16x averaging enabled
V
REFIN
= 2.048 V
Direct input (no attenuator)
±2
Same range, independent of center point
Endpoint corrected
±0.75
±0.4
1
-4
2
50
2
2.5
60
40
2.043
2.048
−0.25
0.25
2
60
2.053
Sourcing Current, I
REFOUTMA X
= -200µA
Sinking Current, I
REFOUTMA X
= 100µA
Per mA
DC
100 mV step in 20 ns with 50 pF load
No load
Sourcing current, I
DACnMAX
= −100 µA
Sinking current, I
DACnMAX
= 100 µA
Capacitor required for decoupling, stability
Per 100 µA
DC
1
11
10.5
500
12.5
12
20
14
13.5
kΩ
V
V
µA
V
V
V
V
mA
mA
kΩ
mA
I
OH
= 0
I
OH
= 1µA
2 V < V
OH
< 7 V
V
PU
(pull-up to VDDCAP or V
PN
) = 2.7 V, I
OH
= 0.5 mA
V
PU
to V
pn
= 6.0 V, I
OH
= 0 mA
V
PU
≤ 2.7 V, I
OH
= 0.5 mA
I
OL
= 20 mA
Maximum sink current per PDO pin
Maximum total sink for all PDOs
Internal pull-up
Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
V
PDO
= 14.4 V
All on-chip time delays derived from this clock
2.4
4.5
V
PU
− 0.3
0
V
OL
I
OL2
I
SINK2
R
PULL-UP
I
SOURCE
(VPn)
2
0.50
20
60
20
2
Three-State Output Leakage Current
Oscillator Frequency
90
100
10
110
µA
kHz
Rev. 0 | Page 5 of 32
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