PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Features
• 56 pin SSOP or 64 pin LQFP package
• On-chip PLL generates output clocks up to
80 MHz (SSOP) or 133.33 MHz (LQFP)
• Zero delay plus multiplier function
• 32 low-skew outputs can eliminate chip-to-chip
skew concerns in systems with less than 33 clocks
• Output to output skew of 200 ps (with stagger)
• Device to device skew of 700ps
• Staggered, fixed skew helps reduce EMI
• Tri-state (Output Enable) pin
• Output blocks can be independently powered off
• 250 ps typical fixed delay between input and
output in “Multiplier” mode
• Ideal for Fast Ethernet and Gigabit Ethernet
designs
• Good for video servers
• 3.3V±5% supply voltage
Description
The MK74ZD133 is a monolithic CMOS high
speed clock driver that includes an on-chip PLL
(Phase Locked Loop). Ideal for communications
and other systems that require a large number of
high-speed clocks, the unique combination of PLL
and 32 outputs can eliminate oscillators and
multiple low skew buffers. With 32 outputs
included in one device, there is also no need to
worry about chip-to-chip skew. The zero delay
modes cause the input clock rising edge to be
synchronized with all of the outputs’ rising edges.
The MK74ZD133 has a large selection of built-in
multipliers, making it possible to run from a clock
input as low as 10 MHz and generate high
frequency outputs up to 80 MHz in the SSOP. For
speeds up to 133.33 MHz, use the LQFP package.
Block Diagram
Optional External Connection to Output 3 (for Zero Delay Mode)
VDD
GND
FBIN
S4:0
5
Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output 1
Output 2
Output 3
Clock input
Input
Buffer
Output
Buffer
Output 32
OE (all outputs)
MDS 74ZD133 C
1
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Pin Assignments
OUT1
OUT2
GND
CLKIN
FBIN
VDD
VDD
FBOUT3
OUT4
GND
OUT5
OUT6
VDD5:8
OUT7
OUT8
GND
OUT9
OUT10
VDD9:12
OUT11
OUT12
GND
VDD13:14
OE
OUT13
OUT14
GND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OUT32/S4
VDD
OUT31/S3
OUT30/S2
OUT29/S1
GND
VDD
OUT28/S0
OUT27
OUT26
OUT25
GND
OUT24
OUT23
VDD21:24
OUT22
OUT21
GND
OUT20
OUT19
VDD
VDD
GND
OUT18
OUT17
OUT16
OUT15
VDD
FBOUT3
OUT4
GND
OUT5
OUT6
VDD5:8
OUT7
OUT8
GND
OUT9
OUT10
VDD9:12
OUT11
OUT12
GND
VDD13:14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
OUT28/S0
OUT27
OUT26
OUT25
GND
OUT24
OUT23
VDD21:24
OUT22
OUT21
GND
OUT20
OUT19
VDD
VDD
Y Package 10mm x 10mm x 1.4mm
F Package 300 mil wide
Controlling the Output Blocks
The MK74ZD133 offers a unique power supply structure that effectively creates five separate blocks of
outputs. The main supply (VDD) goes to all internal circuitry and to 18 outputs, as shown in the Pin
Descriptions table. The other 14 outputs are split into 4 blocks that are powered independently of the main
VDD supply. Each block has its own supply which can be the same as VDD, less than VDD, or left
unpowered to shut off the corresponding outputs. For example, with VDD = 3.3 V, VDD5:8 can be
unconnected and the OUT5:8 levels will be floating. The table below summarizes the power supply control
of the MK74ZD133.
VDD on pins
F Pin # Y Pin # Output Name
VDD Name
VDD5:8
VDD9:12
VDD13:14
VDD21:24
13
19
23
42
6
12
16
40
OUT5:8
OUT9:12
OUT13:14
OUT21:24
F Pin Numbers
11, 12, 14, 15
17, 18, 20, 21
25, 26
40, 41, 43, 44
Y Pin Numbers
4, 5, 7, 8
10, 11, 13, 14
19, 20
38, 39, 41, 42
F Main Supply
6, 7, 28, 29
35, 36, 50, 55
Y Main Supply
24, 25, 33, 34
48, 54, 62, 63
and 64
MDS 74ZD133 C
2
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Pin Descriptions for 56 pin SSOP (F package)
Number
1, 2, 9
3, 10, 16, 22, 27
4
5
6, 7,28,29,35,36,50,55
8
11, 12, 14, 15
13
17, 18, 20, 21
19
23
24
25, 26
30, 31, 32, 33, 37, 38
34, 39, 45, 51
40, 41, 43, 44
42
46, 47, 48
49
52
53
54
56
Name
OUT1, 2, and 4
GND
CLKIN
FBIN
VDD
FBOUT3
OUT5-OUT8
VDD5:8
OUT9-OUT12
VDD9:12
VDD13:14
OE (see note)
OUT13-OUT14
OUT15-OUT20
GND
OUT21-OUT24
VDD21:24
OUT25-OUT27
OUT28/S0
OUT29/S1
OUT30/S2
OUT31/S3
OUT32/S4
Type
O
P
I
I
P
O
O
P
O
P
P
I
O
O
P
O
O
O
I/O
I/O
I/O
I/O
I/O
Description
Clock outputs 1, 2 and 4.
Connect to ground.
Clock input for reference.
Feedback input for "zero delay" in Multiplier Mode.
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
Clock output 3. Connect to pin 5 for Zero Delay Mode.
Clock outputs 5 through 8; level set by VDD5:8 on pin 13.
Power supply for outputs 5 through 8. Cannot exceed VDD.
Clock outputs 9 through 12; level set by VDD9:12 on pin 19.
Power supply for outputs 9 through 12. Cannot exceed VDD.
Power supply for outputs 13 and 14. Cannot exceed VDD.
Output Enable. Tri-states all clock outputs when low. Internal pull-up.
Clock outputs 13 and 14; level set by VDD13:14 on pin 23.
Clock outputs 15 through 20.
Connect to ground.
Clock outputs 21 through 24; level set by VDD21:24 on pin 42.
Power supply for outputs 21 through 24. Cannot exceed VDD.
Clock outputs 25 through 27.
Clock output 28 and output frequency select 0 per table on page 5.
Clock output 29 and output frequency select 1 per table on page 5.
Clock output 30 and output frequency select 2 per table on page 5.
Clock output 31 and output frequency select 3 per table on page 5.
Clock output 32 and output frequency select 4 per table on page 5.
Type: I = Input, O = output, P = power supply connection, I/O=input upon power up, becoming an output
clock within 10 ms later.
Important Note for OE functionality:
To use the output enable function, once the OE has been taken
low, and the outputs have been tri-stated, the VDD must be removed and reapplied for the clocks to run
again.
Staggered output skews for 56 pin SSOP (F)
To aid in the reduction of EMI, and to allow the board
designer the flexibility of running different length traces whose clock edges will still line up at their
destinations, the MK74ZD133F comes with different fixed skews for different outputs. All skews are with
respect to OUT1 (pin 1), and are measured into 33Ω termination resistors with 15 pF capacitive loads.
Output Name
OUT2, OUT25:32
OUT4, OUT18:24
OUT3, OUT5:8, OUT13:17
OUT9:12
Pin Numbers
2, 46:49, 52:54, 56
9, 33, 37, 38, 40, 41, 43, 44
8, 11, 12, 14, 15, 25, 26, 30:32
17, 18, 20, 21
Typical Skew
0
- 350 ps
-225 ps
-150 ps
Maximum variation
200 ps
200 ps
200 ps
200 ps
MDS 74ZD133 C
3
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Pin Descriptions for 64 pin LQFP (Y package)
Number
Name
Type Description
1
FBOUT3
O
Clock output 3. Connect to pin 61 FBIN for Zero Delay Mode.
2, 56, 57
OUT4, 1, and 2
O
Clock outputs 4, 1 and 2 respectively.
3, 9, 15, 21, 30, 32
GND
P
Connect to ground.
4, 5, 7, 8
OUT5-OUT8
O
Clock outputs 5 through 8; level set by VDD5:8 on pin 6.
6
VDD5:8
P
Power supply for outputs 5 through 8. Cannot exceed VDD.
10, 11, 13, 14
OUT9-OUT12
O
Clock outputs 9 through 12; level set by VDD9:12 on pin 12.
12
VDD9:12
P
Power supply for outputs 9 through 12. Cannot exceed VDD.
16
VDD13:14
P
Power supply for outputs 13 and 14. Cannot exceed VDD.
17
OE (see note)
I
Output Enable. Tri-states all clock outputs when low. Internal pull-up.
18, 22, 23, 31
DC
-
Don't Connect. Do not connect anything to these pins.
19, 20
OUT13-OUT14
O
Clock outputs 13 and 14; level set by VDD13:14 on pin 16.
24, 25, 33, 34
VDD
P
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
26, 27, 28, 29, 35, 36 OUT15-OUT20
O
Clock outputs 15 through 20.
37, 43, 49, 50, 58, 59
GND
P
Connect to ground.
38, 39, 41, 42
OUT21-OUT24
O
Clock outputs 21 through 24; level set by VDD21:24 on pin 40.
40
VDD21:24
P
Power supply for outputs 21 through 24. Cannot exceed VDD.
44, 45, 46
OUT25-OUT27
O
Clock outputs 25 through 27.
47
OUT28/S0
I/O Clock output 28 and output frequency select 0 per table on page 5.
48, 54, 62, 63, 64
VDD
P
Power supply for internal circuits and OUT1:4, OUT15:20, and OUT25:32.
51
OUT29/S1
I/O Clock output 29 and output frequency select 1 per table on page 5.
52
OUT30/S2
I/O Clock output 30 and output frequency select 2 per table on page 5.
53
OUT31/S3
I/O Clock output 31 and output frequency select 3 per table on page 5.
55
OUT32/S4
I/O Clock output 32 and output frequency select 4 per table on page 5.
60
CLKIN
I
Clock input for reference.
61
FBIN
I
Feedback input for "zero delay" in Multiplier Mode.
Type: I = Input, O = output, P = power supply connection, I/O=input upon power up, becoming an output clock within 10 ms later.
Important Note for OE functionality:
To use the output enable function, once the OE has been taken low,
and the outputs have been tri-stated, the VDD must be removed and reapplied for the clocks to run again.
Staggered output skews for 64 pin LQFP (Y)
To aid in the reduction of EMI, and to allow the board
designer the flexibility of running different length traces whose clock edges will still line up at their
destinations, the MK74ZD133Y comes with different fixed skews for different outputs. All skews are with
respect to OUT1 (pin 56), and are measured into 33Ω termination resistors with 15 pF capacitive loads.
Output Name
OUT1, OUT25:32
OUT2,3, OUT5:14, OUT23,24
OUT4, OUT15:22
Pin Numbers
56, 44, 45, 46, 47, 51, 52, 53, 55
57, 1, 4, 5, 7, 8,10,11,13,14, 19,20,41,42
2, 26, 27, 28, 29, 35, 36, 38, 39
Typical Skew
0
- 150 ps
- 300 ps
Maximum variation
200 ps
200 ps
200 ps
MDS 74ZD133 C
4
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Output Frequency Generation
Output Frequency Select Table
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input (F)
Input (Y)
Output
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 26.5
3 - 10
4 - 13.33
5 - 16
reserved
10 - 40
6 - 20
20 - 80
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 44.44
3 - 16.67
4 - 22.22
5 - 26.67
reserved
10 - 66.67
6 - 33.33
20 - 100
90*
30
81*
25
54
50
33.33
27
64
75
83.33*
66.66
133.33*
62.5
31.25
125*
55
53.125
135*
106.25*
106*
106.25*
106.66*
107*
x3
x8
x6
x5
reserved
x2
x4
x1
The MK74ZD133 has two primary
modes of operation: “Clock Generator”
and “Zero Delay Multiplier”.
In Clock Generator mode, addresses 0
through 23, specific output frequencies
are generated from a 20 MHz input.
There is no fixed phase relationship
between the input and output clocks.
In Zero Delay Multiplier mode,
addresses 24 through 31, the output
frequency is a simple integer multiple of
the input. The input range can vary over
several MHz, making it possible to
generate output frequencies that are not
included in Clock Generator mode. In
this mode, FBOUT3 is fed back to the
FBIN pin, and the rising edges of the
input and outputs are synchronized.
Configuring the Input/Output
Pins
The MK74ZD133 uses I/O pins whose
status as select inputs are sampled upon
power-up. The chip then selects this
address in the table to the left, and stays
in that configuration until a new power-
up sequence, when the select inputs are
sampled again. These pins all have
internal pull-up resistors, so the 10kΩ
resistor is only needed to connect to
ground for the 0 selection in the table
(as shown below).
33Ω
* These modes only guaranteed in the Y (LQFP) package
For select
= 0 (low)
I/O
to load
10kΩ
Don’t stuff 10k
for“1” selection
MDS 74ZD133 C
5
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
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