MK74ZD133FT datasheet, PDF - EEWORLD Datasheet

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MK74ZD133FT: DescriptionPLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PDSO56, 0.300 INCH, SSOP-56; Categorylogic logic; File Size115KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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MK74ZD133FT Overview

PLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PDSO56, 0.300 INCH, SSOP-56

MK74ZD133FT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	56
Reach Compliance Code	compliant
series	ZD
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	18.415 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	56
Actual output times	32
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	2.794 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
minfmax	80 MHz

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PRELIMINARY INFORMATION

MK74ZD133

PLL and 32-Output Clock Driver

Features

• 56 pin SSOP or 64 pin LQFP package

• On-chip PLL generates output clocks up to

80 MHz (SSOP) or 133.33 MHz (LQFP)

• Zero delay plus multiplier function

• 32 low-skew outputs can eliminate chip-to-chip

skew concerns in systems with less than 33 clocks

• Output to output skew of 200 ps (with stagger)

• Device to device skew of 700ps

• Staggered, fixed skew helps reduce EMI

• Tri-state (Output Enable) pin

• Output blocks can be independently powered off

• 250 ps typical fixed delay between input and

output in “Multiplier” mode

• Ideal for Fast Ethernet and Gigabit Ethernet

designs

• Good for video servers

• 3.3V±5% supply voltage

Description

The MK74ZD133 is a monolithic CMOS high

speed clock driver that includes an on-chip PLL

(Phase Locked Loop). Ideal for communications

and other systems that require a large number of

high-speed clocks, the unique combination of PLL

and 32 outputs can eliminate oscillators and

multiple low skew buffers. With 32 outputs

included in one device, there is also no need to

worry about chip-to-chip skew. The zero delay

modes cause the input clock rising edge to be

synchronized with all of the outputs’ rising edges.

The MK74ZD133 has a large selection of built-in

multipliers, making it possible to run from a clock

input as low as 10 MHz and generate high

frequency outputs up to 80 MHz in the SSOP. For

speeds up to 133.33 MHz, use the LQFP package.

Block Diagram

Optional External Connection to Output 3 (for Zero Delay Mode)

VDD

GND

FBIN

S4:0

Clock

Synthesis

Circuitry

Output

Buffer

Output

Buffer

Output

Buffer

Output 1

Output 2

Output 3

Clock input

Input

Buffer

Output

Buffer

Output 32

OE (all outputs)

MDS 74ZD133 C

Revision 010899

Printed 11/17/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com

MK74ZD133FT Related Products

	MK74ZD133FT	MK74ZD133YT	MK74ZD133F	MK74ZD133Y
Description	PLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PDSO56, 0.300 INCH, SSOP-56	PLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64	PLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PDSO56, 0.300 INCH, SSOP-56	PLL Based Clock Driver, ZD Series, 32 True Output(s), 0 Inverted Output(s), CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	SSOP	QFP	SSOP	QFP
package instruction	SSOP,	LFQFP,	SSOP,	LFQFP,
Contacts	56	64	56	64
Reach Compliance Code	compliant	compliant	compliant	compliant
series	ZD	ZD	ZD	ZD
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G56	S-PQFP-G64	R-PDSO-G56	S-PQFP-G64
JESD-609 code	e0	e0	e0	e0
length	18.415 mm	10 mm	18.415 mm	10 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1
Number of terminals	56	64	56	64
Actual output times	32	32	32	32
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	LFQFP	SSOP	LFQFP
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE, SHRINK PITCH	FLATPACK, LOW PROFILE, FINE PITCH	SMALL OUTLINE, SHRINK PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	225	NOT SPECIFIED	225	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns	0.2 ns	0.2 ns	0.2 ns
Maximum seat height	2.794 mm	1.6 mm	2.794 mm	1.6 mm
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.5 mm	0.635 mm	0.5 mm
Terminal location	DUAL	QUAD	DUAL	QUAD
Maximum time at peak reflow temperature	30	NOT SPECIFIED	30	NOT SPECIFIED
width	7.5 mm	10 mm	7.5 mm	10 mm
minfmax	80 MHz	133.34 MHz	80 MHz	133.34 MHz

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