K6T0808C1D Family
Document Title
32Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No History
0.0
0.1
Initial draft
First revision
-
K
M62256DL/DLI I
SB1
= 100
→
50µA
KM62256DL-L I
SB1
= 20
→
10µA
KM62256DLI-L I
SB1
= 50
→
15µA
- C
IN
= 6
→
8pF, C
IO
= 8
→
10pF
- KM62256D-4/5/7 Family
tOH = 5
→
10ns
- KM62256DL/DLI I
DR
= 50→30µA
KM62256DL-L/DLI-L I
DR
= 30
→
15µA
Finalize
- Remove I
CC
write value
- Improved operating current
I
CC2
= 70
→
60mA
- Improved standby current
KM62256DL/DLI I
SB1
= 50
→
30µA
KM62256DL-L I
SB1
= 10
→
5µA
KM62256DLI-L I
SB1
= 15
→
5µA
- Improved data retention current
KM62256DL/DLI I
DR
= 30
→
5µA
KM62256DL-L/DLI-L I
DR
= 15
→
3µA
- Remove 45ns part from commercial product and 100ns part
from industrial product.
Replace test load 100pF to 50pF for 55ns part
Draft Data
May 18, 1997
April 1, 1997
Remark
Design target
Preliminily
1.0
November 11, 1997
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
November 1997
K6T0808C1D Family
32Kx8 bit Low Power CMOS Static RAM
FEATURES
•
•
•
•
•
•
Process Technology : TFT
Organization : 32Kx8
Power Supply Voltage : 4.5~5.5V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 28-DIP-600B, 28-SOP-450
28-TSOP1-0813.4 F/R
CMOS SRAM
GENERAL DESCRIPTION
The K6T0808C1D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The fami-
lies also support low data retention voltage for battery back-
up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
K6T0808C1D-L
K6T0808C1D-B
K6T0808C1D-P
K6T0808C1D-F
1. The parameter is tested with 50pF test load.
Operating Temperature
V
CC
Range
Speed
Standby
(I
SB1
, Max)
30µA
5µA
30µA
5µA
Operating
(Icc
2,
Max)
PKG Type
Commercial (0~70°C)
4.5 to 5.5V
Industrial (-40~85°C)
55
1)
/70ns
28-DIP,28-SOP
28-TSOP1-F/R
60mA
28-SOP
28-TSOP1-F/R
70ns
PIN DESCRIPTION
OE
A11
A9
A8
VCC A13
WE
WE
VCC
A13 A14
A12
A8
A7
A6
A9
A5
A4
A11
A3
OE
A10
CS
A3
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
FUNCTIONAL BLOCK DIAGRAM
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A13
A8
A12
A14
A4
A5
A6
A7
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS
A10
Clk gen.
Precharge circuit.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
28-TSOP
Type1 - Forward
23
22
21
20
19
18
17
16
15
Row
select
Memory array
256 rows
128×8 columns
28-DIP
28-SOP
22
21
20
19
18
17
16
15
A4
A5
A6
I/O8
A7
I/O7 A12
A14
I/O6 VCC
I/O5
I/O4
WE
A13
A8
A9
A11
OE
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
28-TSOP
Type1 - Reverse
21
22
23
24
25
26
27
28
Data
cont
A10 A3
A0
A1 A2 A9
A11
Pin Name
CS
OE
WE
A
0
~A
14
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Pin Name
I/O
1
~I/O
8
Vcc
Vss
NC
Function
Data Inputs/Outputs
Power
Ground
No connect
CS
WE
OE
Control
Logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
Revision 1.0
November 1997
K6T0808C1D Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6T0808C1D-DL55
K6T0808C1D-DB55
K6T0808C1D-DL70
K6T0808C1D-DB70
K6T0808C1D-GL55
K6T0808C1D-GB55
K6T0808C1D-GL70
K6T0808C1D-GB70
K6T0808C1D-TL55
K6T0808C1D-TB55
K6T0808C1D-TL70
K6T0808C1D-TB70
K6T0808C1D-RL55
K6T0808C1D-RB55
K6T0808C1D-RL70
K6T0808C1D-RB70
Function
28-DIP, 55ns, L-pwr
28-DIP, 55ns, LL-pwr
28-DIP, 70ns, L-pwr
28-DIP, 70ns, LL-pwr
28-SOP, 55ns, L-pwr
28-SOP, 55ns, LL-pwr
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP1 F, 55ns, L-pwr
28-TSOP1 F, 55ns, LL-pwr
28-TSOP1 F, 70ns, L-pwr
28-TSOP1 F, 70ns, LL-pwr
28-TSOP1 R, 55ns, L-pwr
28-TSOP1 R, 55ns, LL-pwr
28-TSOP1 R, 70ns, L-pwr
28-TSOP1 R, 70ns, LL-pwr
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
K6T0808C1D-GP70
K6T0808C1D-GF70
K6T0808C1D-TP70
K6T0808C1D-TF70
K6T0808C1D-RP70
K6T0808C1D-RF70
Function
28-SOP, 70ns, L-pwr
28-SOP, 70ns, LL-pwr
28-TSOP1 F, 70ns, L-pwr
28-TSOP1 F, 70ns, LL-pwr
28-TSOP1 R, 70ns, L-pwr
28-TSOP1 R, 70ns, LL-pwr
FUNCTIONAL DESCRIPTION
CS
H
L
L
L
OE
X
1)
H
L
X
1)
WE
X
1)
H
H
L
I/O
High-Z
High-Z
Dout
Din
Mode
Deselected
Output Disabled
Read
Write
Power
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Ratings
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
260°C, 10sec (Lead Only)
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
K6T0808C1D-L
K6T0808C1D-P
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 1.0
November 1997
K6T0808C1D Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Min
4.5
0
2.2
-0.5
3)
Typ
5.0
0
-
-
CMOS SRAM
Max
5.5
0
Vcc+0.5V
2)
0.8
Unit
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified
Industrial Product : T
A
=-40 to 85°C, otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled not, 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS=V
IH
or OE=V
IH
or WE=V
IL
, V
IO
=V
SS
to Vcc
I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100% duty, I
IO
=0mA
CS≤0.2V, V
IN
≤0.2V,
V
IN
≥Vcc
-0.2V
Read
Write
-
-
2.4
-
Low Power
Low Low Power
-
-
Test Conditions
Min
-1
-1
-
-
Typ
-
-
5
2
-
45
-
-
-
1
0.2
Max
1
1
10
5
20
60
0.4
-
1
30
5
mA
V
V
mA
µA
µA
Unit
µA
µA
mA
mA
Cycle time=Min,100% duty, I
IO
=0mA, CS=V
IL,
V
IN
=V
IH
or V
IL
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH
, Other inputs=V
IH
or V
IL
CS≥Vcc-0.2V, Other inputs=0~Vcc
Revision 1.0
November 1997
K6T0808C1D Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
=50pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(Vcc=4.5~5.5V, K6T0808C1D-L Family:T
A
=0 to 70°C, K6T0808C1D-P Family:T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
55
1)
ns
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
1. The parameter is tested with 50pF test load.
70ns
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
Max
-
70
70
35
-
-
30
30
-
-
-
-
-
-
-
25
-
-
-
Units
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS≥Vcc-0.2V
Vcc=3.0V, CS≥Vcc-0.2V
L-Ver
LL-Ver
See data retention waveform
Min
2.0
-
-
0
5
Typ
-
1
0.2
-
-
Max
5.5
15
3
-
-
ms
Unit
V
µA
Revision 1.0
November 1997
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