32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Release to final Data Sheet.
1. Delete Preliminary
Update A.C parameters
2.1. Updated A.C parameters
Previous spec.
Updated spec.
(12/15/20ns part)
(12/15/20ns part)
t
OE
- / 8/10ns
- / 7 /9 ns
t
CW
- /12/ - ns
- /11/ - ns
t
HZ
8/10/10ns
6/ 7/10ns
t
OHZ
- / 8 / - ns
- / 7 / - ns
t
DW
- / 9 / - ns
- / 8 / - ns
2.2. Add V
OH1
=3.95V with the test condition as Vcc=5V±5% at 25°C
Items
Rev. 3.0
3.1. Add 28-TSOP1 Package.
3.2. Add L-version.
3.3. Add Data Rentention Characteristics.
4.1. Delete DIP Package.
4.2. Delete L-version.
4.3. Delete Data Retention Characteristics and Waveform.
Feb. 22th, 1996
Final
Draft Data
Apr. 1st, 1994
May 14th,1994
Remark
Preliminary
Final
Rev. 2.0
Oct. 4th, 1994
Final
Rev. 4.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
February 1998
PRELIMINARY
K6E0808C1C-C
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 40mA(Max.)
(CMOS) : 2mA(Max.)
Operating K6E0808C1C-12 : 165mA(Max.)
K6E0808C1C-15 : 150mA(Max.)
K6E0808C1C-20 : 140mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
K6E0808C1C-J : 28-SOJ-300
K6E0808C1C-T : 28-TSOP1-0813. 4F
CMOS SRAM
GENERAL DESCRIPTION
The K6E0808C1C is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
K6E0808C1C uses 8 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6E0808C1C is packaged
in a 300mil 28-pin plastic SOJ or TSOP1 forward.
PIN CONFIGURATION
(Top View)
OE
A
11
A
9
A
8
A
13
WE
Vcc
A
14
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CS
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
Vss
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
TSOP1
FUNCTIONAL BLOCK DIAGRAM
A
14
1
A
12
2
28 Vcc
27 WE
26 A
13
25 A
8
24 A
9
23 A
11
Clk Gen.
A
3
A
4
A
5
A
6
A
7
A
8
A
12
A
13
A
14
Pre-Charge-Circuit
A
7
3
A
6
4
A
5
5
Row Select
A
4
6
Memory Array
512 Rows
64x8 Columns
A
3
7
A
2
8
A
1
9
A
0
10
I/O
1
11
SOJ
22 OE
21 A
10
20 CS
19 I/O
8
18 I/O
7
17 I/O
6
16 I/O
5
15 I/O
4
I/O
1
~I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
I/O
2
12
I/O
3
13
Vss 14
PIN FUNCTION
A
0
A
1
A
2
A
9
A
10
A
11
Pin Name
CS
WE
OE
A
0
- A
14
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
-2-
Rev 4.0
February 1998
PRELIMINARY
K6E0808C1C-C
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Rating
-0.5 to 7.0
-0.5 to 7.0
1.0
-65 to 150
0 to 70
Unit
V
V
W
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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