K4E660412D,K4E640412D
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated
using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4E660412D-JC/L(3.3V, 8K Ref., SOJ)
- K4E640412D-JC/L(3.3V, 4K Ref., SOJ)
- K4E660412D-TC/L(3.3V, 8K Ref., TSOP)
- K4E640412D-TC/L(3.3V, 4K Ref., TSOP)
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
•
Active Power Dissipation
Unit : mW
Speed
-45
-50
-60
•
Refresh Cycles
Part
NO.
K4E660412D*
K4E640412D
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
4K
432
396
360
8K
324
288
252
FUNCTIONAL BLOCK DIAGRAM
Refresh Control
Refresh Counter
Memory Array
16,777,216 x 4
Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
•
Performance Range
Speed
-45
-50
-60
Refresh Timer
Row Decoder
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
74ns
84ns
104ns
t
HPC
17ns
20ns
25ns
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
K4E660412D,K4E640412D
CMOS DRAM
PIN CONFIGURATION
(Top Views)
•
K4E660412D-J
•
K4E640412D-J
V
CC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
V
CC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
V
CC
•
K4E660412D-T
•
K4E640412D-T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
V
SS
(J : 400mil SOJ)
(T : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name
A0 - A12
A0 - A11
DQ0 - 3
V
SS
RAS
CAS
W
OE
V
CC
N.C
Pin Function
Address Inputs(8K Product)
Address Inputs(4K Product)
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+3.3V)
No Connection
K4E660412D,K4E640412D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN,
V
OUT
V
CC
Tstg
P
D
I
OS
Address
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
50
CMOS DRAM
Units
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3
*2
Typ
3.3
0
-
-
Max
3.6
0
Vcc+0.3
*1
0.8
Units
V
V
V
V
*1 : Vcc+1.3V at pulse width≤15ns which is measured at V
CC
*2 : -1.3 at pulse width≤15ns which is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
CC
+0.3V,
all other pins not under test=0 Volt)
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-2mA)
Output Low Voltage Level(I
OL
=2mA)
Symbol
I
I(L)
I
O(L)
V
OH
V
OL
Min
-5
-5
2.4
-
Max
5
5
-
0.4
Units
uA
uA
V
V
K4E660412D,K4E640412D
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
Power
Speed
K4E660412D
I
CC1
Don′t care
Normal
L
Don′t care
-45
-50
-60
Don′t care
-45
-50
-60
-45
-50
-60
Don′t care
-45
-50
-60
Don′t care
Don′t care
90
80
70
1
1
90
80
70
100
90
80
0.5
200
120
110
100
350
350
Max
K4E640412D
120
110
100
1
1
120
110
100
100
90
80
0.5
200
120
110
100
350
350
CMOS DRAM
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
mA
uA
uA
I
CC2
I
CC3
I
CC4
Don′t care
Normal
L
Don′t care
L
L
I
CC5
I
CC6
I
CC7
I
CCS
I
CC1
* : Operating Current (RAS and CAS, Address cycling @
t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS, Address cycling @
t
RC
=min.)
I
CC4
* : Extended Data Out Mode Current (RAS=V
IL
, CAS, Address cycling @
t
HPC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @
t
RC
=min)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=CAS-before-RAS cycling or 0.2V
W, OE=V
IH
, Address=Don′t care, DQ=Open, T
RC
=31.25us
I
CCS
: Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=V
CC
-0.2V or 0.2V, DQ0 ~ DQ3=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
K4E660412D,K4E640412D
CAPACITANCE
(T
A
=25°C, V
CC
=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ3]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 2)
Test condition : V
CC
=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Symbol
Min
-45
Max
Min
84
113
45
12
23
3
3
3
1
25
45
8
35
7
11
9
5
0
7
0
7
23
0
0
0
7
6
8
7
0
5K
33
22
10K
50
13
3
3
3
1
30
50
8
38
8
11
9
5
0
7
0
7
25
0
0
0
7
7
8
7
0
10K
37
25
10K
50
13
50
13
25
3
3
3
1
40
60
10
40
10
14
12
5
0
10
0
10
30
0
0
0
10
10
10
10
0
10K
45
30
10K
50
13
-50
Max
Min
104
138
60
15
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
8
8
16
4
10
3,4,10,12
3,4,5,12
3,10,12
3
6,13
3
2
Units
Note
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
OLZ
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
74
101
Electronics Design Contest
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