LDM-ACT-18 datasheet, PDF - EEWORLD Datasheet

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LDM-ACT-18: DescriptionActive Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11; Categorylogic logic; File Size37KB，1 Pages; ManufacturerEngineered Components Co.

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LDM-ACT-18 Overview

Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11

LDM-ACT-18 Parametric

Parameter Name	Attribute value
Maker	Engineered Components Co.
Parts packaging code	DMA
package instruction	QIP, DIP16,.3
Contacts	16/11
Reach Compliance Code	unknown
Other features	INPUT TO 1ST TAP DELAY = 6NS; INTERNAL TERMINATION; MAX RISE TIME CAPTURED
series	ACT
JESD-30 code	R-XDMA-P11
length	22.86 mm
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	11
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	QIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	5 V
programmable delay line	NO
Prop。Delay @ Nom-Sup	18 ns
Certification status	Not Qualified
Maximum seat height	6.096 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	DUAL
Total delay nominal (td)	18 ns
width	10.16 mm

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Advanced CMOS Logic Delay Module

The Advanced CMOS Logic Delay Modules manufactured by Engineered Components Company are designed

to provide output waveforms that reproduce the input waveform after a set amount of delay time has elapsed.

The five output waveforms are delay line taps provided at 20% increments of the total delay

(20, 40, 60, 80, and 100%). These delay modules are non-inverting. The delay times are calibrated to the

listed tolerances on the rising edge delays. The products with a total delay of less than 30ns have additional

delay present at tap 1 due to internal propagation delays (see the Product Selection Table).

The MTBF on these modules, when calculated per MIL-HDBK-217, for a 50 deg.C ground fixed environment and

with 50VDC applied, is in excess of 1.3 million hours. The temperature coefficient of delay is less than

500 ppm/deg.C over the operating temperature range of -40 to +85 deg. C.

The module is provided in a 16-pin DIP package, fully encapsulated in epoxy resin and is housed in a Diallyl

Phthalate case, blue in color. The case marking is applied by silkscreen using white epoxy paint. The 11

copper leads are tin-lead plated and meet the solderability requirements of MIL-STD-202, Method 208.

BLOCK DIAGRAM

12,13

MECHANICAL DIAGRAM

Output

Buffer

Input

Buffer

.150 TYP.

Delay Line

Output Output Output Output

Buffer Buffer Buffer Buffer

.060 TYP.

.300

.020 DIA. TYP.

.350 TYP.

.050 TYP.

4,5

.100 TYP.

.240

Product Selection Table

Part

Output Delay and Tolerances (in ns)

Number

Tap 1(20%) Tap 2 (40%) Tap 3 (60%) Tap 4 (80%) Tap 5 (100%)

LDM-ACT-10

6.0+/-1.0

7.0+/-1.0

8.0+/-1.0

9.0+/-1.0

10.0+/-1.0

LDM-ACT-14

6.0+/-1.0

8.0+/-1.0 10.0+/-1.0 12.0+/-1.0

14.0+/-1.0

LDM-ACT-18

6.0+/-1.0

9.0+/-1.0 12.0+/-1.0 15.0+/-1.0

18.0+/-1.0

LDM-ACT-22

6.0+/-1.0 10.0+/-1.0 14.0+/-1.0 18.0+/-1.0

22.0+/-1.0

LDM-ACT-26

6.0+/-1.0 11.0+/-1.0 16.0+/-1.0 21.0+/-1.0

26.0+/-1.0

LDM-ACT-30

6.0+/-1.0 12.0+/-1.0 18.0+/-1.0 24.0+/-1.0

30.0+/-1.5

LDM-ACT-35

7.0+/-1.0 14.0+/-1.0 21.0+/-1.0 28.0+/-1.5

35.0+/-1.5

LDM-ACT-40

8.0+/-1.0 16.0+/-1.0 24.0+/-1.0 32.0+/-1.5

40.0+/-2.0

LDM-ACT-45

9.0+/-1.0 18.0+/-1.0 27.0+/-1.5 36.0+/-1.5

45.0+/-2.0

LDM-ACT-50

10.0+/-1.0 20.0+/-1.0 30.0+/-1.5 40.0+/-2.0

50.0+/-2.0

LDM-ACT-55

11.0+/-1.0 22.0+/-1.0 33.0+/-1.5 44.0+/-2.0

55.0+/-2.0

LDM-ACT-60

12.0+/-1.0 24.0+/-1.0 36.0+/-1.5 48.0+/-2.0

60.0+/-2.0

LDM-ACT-65

13.0+/-1.0 26.0+/-1.5 39.0+/-1.5 52.0+/-2.0

65.0+/-2.5

LDM-ACT-70

14.0+/-1.0 28.0+/-1.5 42.0+/-2.0 56.0+/-2.0

70.0+/-2.5

LDM-ACT-75

15.0+/-1.0 30.0+/-1.5 45.0+/-2.0 60.0+/-2.0

75.0+/-2.5

LDM-ACT-80

16.0+/-1.0 32.0+/-1.5 48.0+/-2.0 64.0+/-2.5

80.0+/-3.0

LDM-ACT-85

17.0+/-1.0 34.0+/-1.5 51.0+/-2.0 68.0+/-2.5

85.0+/-3.0

LDM-ACT-90

18.0+/-1.0 36.0+/-1.5 54.0+/-2.0 72.0+/-2.5

90.0+/-3.0

LDM-ACT-95

19.0+/-1.0 38.0+/-1.5 57.0+/-2.0 76.0+/-2.5

95.0+/-3.0

LDM-ACT-100

20.0+/-1.0 40.0+/-1.5 60.0+/-2.0 80.0+/-3.0 100.0+/-3.0

LDM-ACT-125

25.0+/-1.0 50.0+/-2.0 75.0+/-2.5 100.0+/-3.0 125.0+/-4.0

LDM-ACT-150

30.0+/-1.5 60.0+/-2.0 90.0+/-3.0 120.0+/-4.0 150.0+/-5.0

LDM-ACT-175

35.0+/-1.5 70.0+/-2.5 105.0+/-4.0 140.0+/-4.5 175.0+/-5.0

LDM-ACT-200

40.0+/-1.5 80.0+/-3.0 120.0+/-4.0 160.0+/-5.0 200.0+/-6.0

LDM-ACT-225

45.0+/-2.0 90.0+/-3.0 135.0+/-4.0 180.0+/-6.0 225.0+/-7.0

LDM-ACT-250

50.0+/-2.0 100.0+/-3.0 150.0+/-5.0 200.0+/-6.0 250.0+/-8.0

Special modules can often be manufactured to provide for customer specific applications.

.400

LDM-ACT-26

1 2 C C 3 4 OUT

Operating Specifications:

All measurements made at 25 deg. C

All measurements made with Vcc = +5VDC

All measurements made with (1) ACT output load

Operating Temperature: -40 to +85 deg. C

Storage Temperature: -55 to +125 deg. C

Vcc Supply Voltage: 4.75 to 5.25VDC

Vcc Supply Current:

Constant “0” or “1” in = 1nA typical

Constant 1 MHz square wave in = 4mA typical

Logic “High” Input:

Voltage: 2.0VDC min. ; Vcc max.

Logic “Low” Input:

Voltage: 0.8 VDC max.

Logic “High” Voltage Out: 4.3VDC min. @ -24mA

Logic “Low” Voltage Out: 0.44VDC max. @ +24mA

engineered components company

A Division of Cornucopia Tool & Plastics, Inc. PO Box 1915, 448 Sherwood Rd., Paso Robles CA 93447

YYWW

.030

DATE CODE

V V

+/-.020

.165

Top view

.900

Phone: 805-369-0034

Fax:

805-369-0033

Web: www.ec2.com

LDM-ACT-18 Related Products

	LDM-ACT-18	LDM-ACT-40	LDM-ACT-85	LDM-ACT-90	LDM-ACT-95
Description	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11	Active Delay Line, 1-Func, 5-Tap, True Output, CMOS, 0.240 INCH HEIGHT, DIP-16/11
Maker	Engineered Components Co.	Engineered Components Co.	Engineered Components Co.	Engineered Components Co.	Engineered Components Co.
Parts packaging code	DMA	DMA	DMA	DMA	DMA
package instruction	QIP, DIP16,.3	QIP, DIP16,.3	QIP, DIP16,.3	QIP, DIP16,.3	QIP, DIP16,.3
Contacts	16/11	16/11	16/11	16/11	16/11
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
Other features	INPUT TO 1ST TAP DELAY = 6NS; INTERNAL TERMINATION; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED	TAP TO TAP DELAY TOL.[NS] VARIES; MAX RISE TIME CAPTURED
series	ACT	ACT	ACT	ACT	ACT
JESD-30 code	R-XDMA-P11	R-XDMA-P11	R-XDMA-P11	R-XDMA-P11	R-XDMA-P11
length	22.86 mm	22.86 mm	22.86 mm	22.86 mm	22.86 mm
Logic integrated circuit type	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE
Number of functions	1	1	1	1	1
Number of taps/steps	5	5	5	5	5
Number of terminals	11	11	11	11	11
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	QIP	QIP	QIP	QIP	QIP
Encapsulate equivalent code	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	5 V	5 V	5 V	5 V	5 V
programmable delay line	NO	NO	NO	NO	NO
Prop。Delay @ Nom-Sup	18 ns	40 ns	85 ns	90 ns	95 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	6.096 mm	6.096 mm	6.096 mm	6.096 mm	6.096 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Total delay nominal (td)	18 ns	40 ns	85 ns	90 ns	95 ns
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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