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JANSR2N7483T3

Description
Power Field-Effect Transistor, 18A I(D), 60V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, HERMETIC SEALED, CERAMIC PACKAGE-3
CategoryDiscrete semiconductor    The transistor   
File Size204KB,22 Pages
ManufacturerInfineon
Websitehttp://www.infineon.com/
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JANSR2N7483T3 Overview

Power Field-Effect Transistor, 18A I(D), 60V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, HERMETIC SEALED, CERAMIC PACKAGE-3

JANSR2N7483T3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerInfineon
package instructionHERMETIC SEALED, CERAMIC PACKAGE-3
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresULTRA-LOW RESISTANCE
Avalanche Energy Efficiency Rating (Eas)110 mJ
Shell connectionISOLATED
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage60 V
Maximum drain current (Abs) (ID)18 A
Maximum drain current (ID)18 A
Maximum drain-source on-resistance0.04 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-257AA
JESD-30 codeR-CSFM-P3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeRECTANGULAR
Package formFLANGE MOUNT
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)75 W
Maximum pulsed drain current (IDM)72 A
Certification statusQualified
GuidelineMIL-19500; RH - 100K Rad(Si)
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
The documentation and process conversion
measures necessary to comply with this revision
shall be completed by 21 August 2010.
INCH-POUND
MIL-PRF-19500/702C
21 May 2010
SUPERSEDING
MIL-PRF-19500/702B
30 May 2007
PERFORMANCE SPECIFICATION SHEET
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED
(TOTAL DOSE AND SINGLE EVENT EFFECTS)
TRANSISTOR, N-CHANNEL, SILICON, TYPES 2N7482T3, 2N7483T3, AND 2N7484T3,
JANTXVR, F, G, AND H AND JANSR, F, G, AND H
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for an N-Channel, enhancement-mode,
MOSFET, radiation hardened (total dose and single event effects (SEE)), power transistor. Two levels of product
assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy maximum rating
(E
AS
) and maximum avalanche current (I
AS
). See 6.5 for JANHC and JANKC die versions.
1.2 Physical dimensions. See figure 1, (TO-257AA, T3).
1.3 Maximum ratings. T
A
= +25°C, unless otherwise specified.
Type
P
T
(1)
T
C
=
+25°C
W
2N7482T3
2N7483T3
2N7484T3
75
75
75
P
T
T
A
=
+25°C
W
1.56
1.56
1.56
R
θJC
(2)
V
DS
V
DG
V
GS
I
D1
(3) (4)
T
C
= +25°C
I
D2
(3) (4)
T
C
=
+100°C
A dc
18
18
14
I
S
I
DM
(5)
T
J
and
T
STG
°C
-55
to
+150
°C/W
1.67
1.67
1.67
V dc
30
60
100
V dc
30
60
100
V dc
±20
±20
±20
A dc
18
18
18
A dc
18
18
18
A (pk)
72
72
72
(1) Derate linearly 0.6 W/°C for T
C
> +25°C.
(2) See figure 2, thermal impedance curves.
(3) The
following formula derives the maximum theoretical I
D
specs. I
D
is limited to 18A by package
and device construction.
I
D
=
(
R
θ
JC
T
JM
- T
C
)
x
(
R
DS
( on ) at T
JM
)
(4) See figure 3, maximum drain current graph.
(5) I
DM
= 4 X I
D1
, as defined in note (3).
* Comments, suggestions, or questions on this document should be addressed to Defense Supply Center,
Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to
Semiconductor@dscc.dla.mil.
Since contact information can change, you may want to verify the currency of
this address information using the ASSIST Online database at
https://assist.daps.dla.mil/.
AMSC N/A
FSC 5961

JANSR2N7483T3 Related Products

JANSR2N7483T3 JANTXVR2N7482T3 JANTXVR2N7483T3 JANSH2N7484T3 JANSH2N7482T3
Description Power Field-Effect Transistor, 18A I(D), 60V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, HERMETIC SEALED, CERAMIC PACKAGE-3 Power Field-Effect Transistor, 18A I(D), 30V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN Power Field-Effect Transistor, 18A I(D), 60V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN Power Field-Effect Transistor, 18A I(D), 100V, 0.07ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN Power Field-Effect Transistor, 18A I(D), 30V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, HERMETIC SEALED, CERAMIC PACKAGE-3 PIN
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible
Maker Infineon Infineon Infineon Infineon Infineon
package instruction HERMETIC SEALED, CERAMIC PACKAGE-3 TO-257AA, 3 PIN TO-257AA, 3 PIN TO-257AA, 3 PIN HERMETIC SEALED, CERAMIC PACKAGE-3 PIN
Reach Compliance Code unknown unknown unknown unknown unknown
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
Avalanche Energy Efficiency Rating (Eas) 110 mJ 117 mJ 110 mJ 87 mJ 177 mJ
Configuration SINGLE WITH BUILT-IN DIODE SINGLE SINGLE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 60 V 30 V 60 V 100 V 30 V
Maximum drain current (Abs) (ID) 18 A 18 A 18 A 18 A 18 A
Maximum drain current (ID) 18 A 18 A 18 A 18 A 18 A
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JEDEC-95 code TO-257AA TO-257AA TO-257AA TO-257AA TO-257AA
JESD-30 code R-CSFM-P3 R-XSFM-P3 R-XSFM-P3 S-XSFM-P3 S-CSFM-P3
JESD-609 code e0 e0 e0 e0 e0
Number of components 1 1 1 1 1
Number of terminals 3 3 3 3 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C 150 °C 150 °C 150 °C
Package body material CERAMIC, METAL-SEALED COFIRED UNSPECIFIED UNSPECIFIED UNSPECIFIED CERAMIC, METAL-SEALED COFIRED
Package shape RECTANGULAR RECTANGULAR RECTANGULAR SQUARE SQUARE
Package form FLANGE MOUNT FLANGE MOUNT FLANGE MOUNT FLANGE MOUNT FLANGE MOUNT
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 75 W 75 W 75 W 75 W 75 W
Maximum pulsed drain current (IDM) 72 A 72 A 72 A 72 A 72 A
Certification status Qualified Qualified Qualified Qualified Qualified
surface mount NO NO NO NO NO
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form PIN/PEG PIN/PEG PIN/PEG PIN/PEG PIN/PEG
Terminal location SINGLE SINGLE SINGLE SINGLE SINGLE
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Transistor component materials SILICON SILICON SILICON SILICON SILICON
Other features ULTRA-LOW RESISTANCE RADIATION HARDENED RADIATION HARDENED - -
Shell connection ISOLATED ISOLATED ISOLATED ISOLATED -
Maximum drain-source on-resistance 0.04 Ω - - 0.07 Ω 0.03 Ω
Guideline MIL-19500; RH - 100K Rad(Si) MIL-19500/702 MIL-19500/702 - -
transistor applications SWITCHING - - SWITCHING SWITCHING
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