JANSH2N7484T3 datasheet, PDF - EEWORLD Datasheet

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JANSH2N7484T3: DescriptionPower Field-Effect Transistor, 18A I(D), 100V, 0.07ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN; CategoryDiscrete semiconductor The transistor; File Size204KB，22 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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JANSH2N7484T3 Overview

Power Field-Effect Transistor, 18A I(D), 100V, 0.07ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN

JANSH2N7484T3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Infineon
package instruction	TO-257AA, 3 PIN
Reach Compliance Code	unknown
ECCN code	EAR99
Avalanche Energy Efficiency Rating (Eas)	87 mJ
Shell connection	ISOLATED
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	100 V
Maximum drain current (Abs) (ID)	18 A
Maximum drain current (ID)	18 A
Maximum drain-source on-resistance	0.07 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
JEDEC-95 code	TO-257AA
JESD-30 code	S-XSFM-P3
JESD-609 code	e0
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	150 °C
Package body material	UNSPECIFIED
Package shape	SQUARE
Package form	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	N-CHANNEL
Maximum power dissipation(Abs)	75 W
Maximum pulsed drain current (IDM)	72 A
Certification status	Qualified
surface mount	NO
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal location	SINGLE
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON

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The documentation and process conversion

measures necessary to comply with this revision

shall be completed by 21 August 2010.

INCH-POUND

MIL-PRF-19500/702C

21 May 2010

SUPERSEDING

MIL-PRF-19500/702B

30 May 2007

PERFORMANCE SPECIFICATION SHEET

SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED

(TOTAL DOSE AND SINGLE EVENT EFFECTS)

TRANSISTOR, N-CHANNEL, SILICON, TYPES 2N7482T3, 2N7483T3, AND 2N7484T3,

JANTXVR, F, G, AND H AND JANSR, F, G, AND H

This specification is approved for use by all Departments

and Agencies of the Department of Defense.

The requirements for acquiring the product described herein shall consist of

this specification sheet and MIL-PRF-19500.

1. SCOPE

1.1 Scope. This specification covers the performance requirements for an N-Channel, enhancement-mode,

MOSFET, radiation hardened (total dose and single event effects (SEE)), power transistor. Two levels of product

assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy maximum rating

) and maximum avalanche current (I

). See 6.5 for JANHC and JANKC die versions.

1.2 Physical dimensions. See figure 1, (TO-257AA, T3).

1.3 Maximum ratings. T

= +25°C, unless otherwise specified.

Type

(1)

+25°C

2N7482T3

2N7483T3

2N7484T3

+25°C

1.56

θJC

(2)

(3) (4)

= +25°C

(3) (4)

+100°C

A dc

(5)

and

STG

°C

-55

+150

°C/W

1.67

V dc

100

V dc

100

V dc

±20

A dc

A (pk)

(1) Derate linearly 0.6 W/°C for T

> +25°C.

(2) See figure 2, thermal impedance curves.

(3) The

following formula derives the maximum theoretical I

specs. I

is limited to 18A by package

and device construction.

(

- T

)

(

( on ) at T

)

(4) See figure 3, maximum drain current graph.

(5) I

= 4 X I

, as defined in note (3).

* Comments, suggestions, or questions on this document should be addressed to Defense Supply Center,

Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to

Semiconductor@dscc.dla.mil.

Since contact information can change, you may want to verify the currency of

this address information using the ASSIST Online database at

https://assist.daps.dla.mil/.

AMSC N/A

FSC 5961

MIL-PRF-19500/702C

3. REQUIREMENTS

3.1 General. The individual item requirements shall be as specified in MIL-PRF-19500 and as modified herein.

3.2 Qualification. Devices furnished under this specification shall be products that are manufactured by a

manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturer's list (QML)

before contract award (see 4.2 and 6.3).

3.3 Abbreviations, symbols, and definitions. Abbreviations, symbols, and definitions used herein shall be as

specified in MIL-PRF-19500.

3.4 Interface and physical dimensions. The interface and physical dimensions shall be as specified in

MIL-PRF-19500 and on figure 1 (TO-257AA, T3) herein.

3.4.1 Lead finish. Unless otherwise specified, lead finish shall be solderable in accordance with

MIL-PRF-19500, MIL-STD-750, and herein. Where a choice of lead finish is desired, it shall be specified in the

acquisition document (see 6.2).

3.4.2 Internal construction. Multiple chip construction shall not be permitted.

3.5 Electrostatic discharge protection. The devices covered by this specification require electrostatic discharge

protection.

3.5.1 Handling. MOS devices must be handled with certain precautions to avoid damage due to the accumulation

of static charge. However, the following handling practices are recommended (see 3.5).

a. Devices should be handled on benches with conductive handling devices.

b. Ground test equipment, tools, and personnel handling devices.

c. Do not handle devices by the leads.

d. Store devices in conductive foam or carriers.

e. Avoid use of plastic, rubber, or silk in MOS areas.

f. Maintain relative humidity above 50 percent if practical.

g. Care should be exercised during test and troubleshooting to apply not more than maximum rated

voltage to any lead.

h. Gate must be terminated to source, R

≤

100 kΩ, whenever bias voltage is to be applied drain to source.

3.6 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance

characteristics are as specified in 1.3, 1.4, and table I herein.

3.7 Electrical test requirements. The electrical test requirements shall be as specified in table I.

3.8 Marking. Marking shall be in accordance with MIL-PRF-19500.

3.9 Workmanship. Semiconductor devices shall be processed in such a manner as to be uniform in quality and

shall be free from other defects that will affect life, serviceability, or appearance.

JANSH2N7484T3 Related Products

	JANSH2N7484T3	JANTXVR2N7482T3	JANTXVR2N7483T3	JANSR2N7483T3	JANSH2N7482T3
Description	Power Field-Effect Transistor, 18A I(D), 100V, 0.07ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN	Power Field-Effect Transistor, 18A I(D), 30V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN	Power Field-Effect Transistor, 18A I(D), 60V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN	Power Field-Effect Transistor, 18A I(D), 60V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, HERMETIC SEALED, CERAMIC PACKAGE-3	Power Field-Effect Transistor, 18A I(D), 30V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, HERMETIC SEALED, CERAMIC PACKAGE-3 PIN
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Infineon	Infineon	Infineon	Infineon	Infineon
package instruction	TO-257AA, 3 PIN	TO-257AA, 3 PIN	TO-257AA, 3 PIN	HERMETIC SEALED, CERAMIC PACKAGE-3	HERMETIC SEALED, CERAMIC PACKAGE-3 PIN
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Avalanche Energy Efficiency Rating (Eas)	87 mJ	117 mJ	110 mJ	110 mJ	177 mJ
Configuration	SINGLE WITH BUILT-IN DIODE	SINGLE	SINGLE	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	100 V	30 V	60 V	60 V	30 V
Maximum drain current (Abs) (ID)	18 A	18 A	18 A	18 A	18 A
Maximum drain current (ID)	18 A	18 A	18 A	18 A	18 A
FET technology	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR
JEDEC-95 code	TO-257AA	TO-257AA	TO-257AA	TO-257AA	TO-257AA
JESD-30 code	S-XSFM-P3	R-XSFM-P3	R-XSFM-P3	R-CSFM-P3	S-CSFM-P3
JESD-609 code	e0	e0	e0	e0	e0
Number of components	1	1	1	1	1
Number of terminals	3	3	3	3	3
Operating mode	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE	ENHANCEMENT MODE
Maximum operating temperature	150 °C	150 °C	150 °C	150 °C	150 °C
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE
Package form	FLANGE MOUNT	FLANGE MOUNT	FLANGE MOUNT	FLANGE MOUNT	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Polarity/channel type	N-CHANNEL	N-CHANNEL	N-CHANNEL	N-CHANNEL	N-CHANNEL
Maximum power dissipation(Abs)	75 W	75 W	75 W	75 W	75 W
Maximum pulsed drain current (IDM)	72 A	72 A	72 A	72 A	72 A
Certification status	Qualified	Qualified	Qualified	Qualified	Qualified
surface mount	NO	NO	NO	NO	NO
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	SINGLE	SINGLE	SINGLE	SINGLE	SINGLE
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Transistor component materials	SILICON	SILICON	SILICON	SILICON	SILICON
Shell connection	ISOLATED	ISOLATED	ISOLATED	ISOLATED	-
Maximum drain-source on-resistance	0.07 Ω	-	-	0.04 Ω	0.03 Ω
transistor applications	SWITCHING	-	-	SWITCHING	SWITCHING
Other features	-	RADIATION HARDENED	RADIATION HARDENED	ULTRA-LOW RESISTANCE	-
Guideline	-	MIL-19500/702	MIL-19500/702	MIL-19500; RH - 100K Rad(Si)	-

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