Image Correction ICs
Image Correction IC
for Camera
BU1571KN
●Description
BU1571KN is AIE : Adaptive Image Enhancer (image processing technology by ROHM’s hardware).
Provides unprecedented visibility under severe conditions, such as darkness or extreme backlighting.
●Features
1) UXGA size (16001200) for input of image data up to 7.5 fps, SXGA size (12801024) for input of image data up to
15 fps and VGA size (640480) for input of image data up to 30 fps.
2) Input data format for YUV=4:2:2 8bit. Order of components may be adjusted by the register.
3) Operation modes are image enhance mode, through mode, and sleep mode.
4) Strength of image correction can be set to linear.
5) Register can be set up with a 2-line serial interface.
*Extra document is prepared separately about each register setup. Please refer to the Development Scheme on page 6.
No.10060ECT01
●Application
Security camera, Intercom with camera, Drive recorder, and Web camera etc.
●Lineup
matrix
Parameter
Supply power source
voltage
1.45-1.55(V
DD
Core)
2.7-3.6(V
DD
Io)
Camera
Interface
Supported up to
Max 2M pixels.
(1600×1200)
Control
Interface
I
2
C BUS
Output
Interface
8bit
YUV=4:2:2
Camera interface
Interrupt
output
-
Package
BU1571KN
VQFN36
●Absolute
maximum ratings
(Ta=25℃)
Symbol
VDDIO
VDD
VIN
Tstg
PD
Ratings
-0.3 ~ +4.2
-0.3 ~ +2.1
-0.3 ~ VDDIO+0.3
-40 ~ +125
450
Unit
V
V
V
℃
mW
Parameter
Supply power source voltage 1
Supply power source voltage 2
Input voltage
Storage temperature range
Power dissipation
*In the case exceeding 25℃, 4.5mW should be reduced
at the rating 1℃.
●Recommended
operating range
Parameter
Supply power source voltage 1(IO)
Supply power source voltage 2(CORE)
Input voltage range
Operating temperature range
*Please supply power source in order of VDD→VDDIO.
Symbol
VDDIO
VDD
VIN-VDDIO
Topr
Ratings
2.70 ~ 3.60(Typ:3.3V)
1.45 ~ 1.55(Typ:1.50V)
0 ~ VDDIO
-40 ~ +85
Unit
V
V
V
℃
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© 2010 ROHM Co., Ltd. All rights reserved.
1/8
2010.06 - Rev.C
BU1571KN
●Electric
characteristics
(Unless otherwise specified, VDD=1.50V,VDDIO=3.3V,GND=0.0V,Ta=25℃,f
IN
=52.0MHz)
Limits
Parameter
Symbol
Unit
MIN.
TYP.
MAX.
Input frequency
Operating consumption current
Static consumption current
Input ”H” current 1
Input ”H” current 2
Input ”L” current 1
Input ”L” current 2
Input ”H” voltage 1
Input ”L” voltage 1
Input ”H” voltage 2
Input ”L” voltage 2
Hysteresis voltage width
Output ”H” voltage
Output ”L” voltage
f
IN
IDD1
IDDst
IIH1
IIH2
IIL1
IIL2
VIH1
VIL1
VIH2
VIL2
Vhys
VOH
VOL
10.0
-
-
-10
35
-10
-10
VDDIO
0.8
-0.3
VDDIO
0.85
-0.3
-
VDDIO
-0.4
0.0
-
15
-
-
70
-
-
-
-
-
-
0.5
-
-
52.0
-
30
10
140
10
10
VDDIO
+0.3
VDDIO
0.2
VDDIO
+0.3
VDDIO
0.15
-
VDDIO
0.4
Technical Note
Condition
MHz CAMCKI(DUTY45% ~ 55%)
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
At enhance mode setting
At sleep mode setting,
input terminal=GND setting
VIH=VDDIO
Pull-Down terminal, VIH=VDDIO
VIL=GND
Pull-Down terminal, VIL=GND
Normal input
(including input mode of I/O terminal)
Normal input
(including input mode of I/O terminal)
Hysteresis input
(RESETB, CAMCKI, SDA, SDC)
Hysteresis input
(RESETB, CAMCKI, SDA, SDC)
Hysteresis input
(RESETB, CAMCKI, SDA, SDC)
IOH=-1.0mA(DC)
(including input mode of I/O terminal)
IOL=1.0mA(DC)
(including input mode of I/O terminal)
●Block
Diagram
●Recommended
Application Circuit
CAMDI[7:0]
8
YUV=4:2:2
Color
Correction
Luminance
Distinction
8
CAMDO[7:0]
YUV=4:2:2
CAMDI[7:0]
CAMDI[7:0]
CAMDO[7:0]
CAMHSO
CAMVSO
CAMDO[7:0]
CAMHSO
CAMVSO
CAMCKO
Image
Processing
IC
CAMHSI
CAMHSI
Image
Enhance
CAMVSI
Camera
Module
CAMCKI
BU1571KN
CAMVSI
CAMCKI
CAMCKO
SDA SDC
SDA
SDC
Serial
Interface
SDA
SDC
CAMHSI
CAMVSI
CAMCKI
CAMHSO
Timing
Generator
CAMVSO
CAMCKO
HOST
CPU
*Extra document is prepared separately about system evaluation. Please refer to the Development Scheme on page 6.
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© 2010 ROHM Co., Ltd. All rights reserved.
2/8
2010.06 - Rev.C
BU1571KN
●Terminal
functions
PIN No. PIN Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CAMVSI
N.C.
CAMHSI
CAMDI0
CAMDI1
CAMDI2
CAMDI3
CAMDI4
CAMDI5
CAMDI6
CAMDI7
VDDIO
CAMCKI
GND
VDD
SDA
SDC
TESTOUT
CAMVSO
N.C.
CAMHSO
CAMDO0
CAMDO1
CAMDO2
CAMDO3
CAMDO4
CAMDO5
CAMDO6
CAMDO7
TEST1
TEST2
RESETB
VDDIO
CAMCKO
GND
VDD
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
-
Out
-
-
-
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Low
Low
Low
PWR
CLK
GND
PWR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Horizontal Timing Signal Output
Data Output: Bit 0
Data Output: Bit 1
Data Output: Bit 2
Data Output: Bit 3
Data Output: Bit 4
Data Output: Bit 5
Data Output: Bit 6
Data Output: Bit 7
Test Mode Terminal 1 (Connect to GND)
Test Mode Terminal 2 (Connect to GND)
System Reset Signal
DIGITAL IO Power Source
Clock Output
Common GROUND
CORE Power Source
In
In
In
In
In
In
In
In
In
-
In
-
-
In/Out
In/Out
Out
Out
*
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
PWR
CLK
GND
PWR
DATA
CLK
High
-
-
-
-
-
-
-
-
-
-
-
-
-
-
In
In
-
-
Horizontal Timing Input (pull-down at sleep mode)
Data Input Bit 0 (pull-down at sleep mode)
Data Input Bit 1 (pull-down at sleep mode)
Data Input Bit 2 (pull-down at sleep mode)
Data Input Bit 3 (pull-down at sleep mode)
Data Input Bit 4 (pull-down at sleep mode)
Data Input Bit 5 (pull-down at sleep mode)
Data Input Bit 6 (pull-down at sleep mode)
Data Input Bit 7 (pull-down at sleep mode)
DIGITAL IO Power Source
Clock Input (pull-down at sleep mode)
Common GROUND
CORE Power Source
In/Output Serial Data
In/Output Serial Clock
TEST Out Pin ( Keep Open )
Vertical Timing Signal Output
In/Out Active Level
In
*
Init
-
Function explanation
Vertical Timing Input (pull-down at sleep mode)
Technical Note
I/O type
B*1
B*1
B*1
B*1
B*1
B*1
B*1
B*1
B*1
B*1
-
D*1
-
-
E
E
-
C
C
C
C
C
C
C
C
C
C
B
B
A
-
C
-
-
*”*” in the Active Level column indicates that it may be changed during set-up of the register. Init indicates pin status when released from reset.
*1: Pull-down is ON during reset (initial status).
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© 2010 ROHM Co., Ltd. All rights reserved.
3/8
2010.06 - Rev.C
BU1571KN
●Equivalent
Circuit Structures of input / output pins
Type
The equivalent circuit structure
VDDIO
Technical Note
Type
The equivalent circuit structure
VDDIO
VDDIO
Internal signal
To internal
A
GND
B
To internal
GND
GND
GND
Input terminal with Schmitt
VDDIO
VDDIO
Input terminal with PULL-DOWN
VDDIO
Internal signal
Internal signal
C
D
GND
GND
GND
GND
To internal
Output terminal
VDDIO
VDDIO
VDDIO
To
internal
Internal signal
Hysteresis input terminal with PULL-DOWN
E
GND
Internal signal
GND
GND
Internal signal
Hysteresis input / output terminal
●Terminal
Layout
(Bottom View)
CAMDI0
CAMVSI
CAMHSI
CAMDI5
CA MDI3
CAMDI1
CAMDI2
CAMDI4
N.C.
VDD
GND
CAMCKO
VDDIO
RESETB
TEST2
TEST1
CAMDO7
CAMDO6
CAMDI6
CAMDI7
VDDIO
CAMCKI
GND
VDD
SDA
SDC
TESTOUT
CAMDO5
CAMDO4
CAMDO3
CAMDO2
CAMDO1
N.C.
CAMDO0
CAMHSO
CAMVSO
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© 2010 ROHM Co., Ltd. All rights reserved.
4/8
2010.06 - Rev.C
BU1571KN
●Timing
Chart
1. Two-line serial interface
1.1 Two-line serial interface timing
SDA
t
SU;DAT
Technical Note
t
LOW
t
HD;ST
t
BUF
SDC
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
Table 1 I
2
C Interface timing
Symbol
f
SCL
t
HD;STA
f
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
Parameter
SDC Clock Frequency
Hold-time(repetition)『START』conditions
(The first clock pulse is generated after this period.)
The "L" period of SDC clock
The "H" period of SDC clock
Setup time of repetitive
『START』conditions
Hold time of SDA
Setup time of SDA
Setup time of the
『STOP』conditions
BUS free time between
『STOP』conditions
and the
『START』conditions
MIN.
0
0.6
1.3
0.6
0.6
0
100
0.6
1.3
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
MAX.
400
-
-
-
-
Unit
kHz
µs
µs
µs
µs
µs
ns
µs
µs
2. Camera module interface
2.1. Camera module interface timing
The input timing of camera image signal on camera I/F is shown in Table 2.
Table 2.
CAMVSI
CAMHSI
CAMDI0
－CAMDI7
CAMCKI
(CKPOL=“1”)
CAMCKI
(CKPOL=“0”)
tCMS
tCMH
BU1571KN timing (Camera data input)
Explanation
CAMCKI Rise / Fall
Camera set-up Time
CAMCKI Rise / Fall
Camera Hold Time
MIN. TYP. MAX. UNIT
4
4
-
-
-
-
ns
ns
Symbol
tCMS
tCMH
The input timing of camera image signal on camera I/F is shown in Table 2.1-2.
tPCLK
CAMCKO
tPHH
CAMVSO
CAMHSO
tPDV
CAMDO[7:0]
Table 2.
Symbol
tPCLK
tPHL
Camera data output timing
Explanation
Clock Cycle
Clock Duty
Decision of CAMDO from
CAMCKO
Decision of CAMVSO or
CAMHSO from CAMCKO
MIN. TYP. MAX. UNIT
19.2
45
-
-
-
50
-
-
-
55
5
5
ns
%
ns
ns
dPCLK
tPDV
tPHL,
tPHH
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© 2010 ROHM Co., Ltd. All rights reserved.
5/8
2010.06 - Rev.C
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