128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No.
1.0
1.1
1.2
1.3
1.4
First Version Release
1. Corrected PIN ASSIGNMENT A12 to NC
1. Changed IDD3P and IDD3PS 3mA to 5mA
2. Added Industrial Temperature (-40
o
C to 85
o
C)
Changed tOH(Only Symbol ‘H’): 2.5ns -> 2.7ns
Add Super Low Power-> IDD6: 500uA
History
Draft Date
Dec. 2004
Jan. 2005
Feb. 2005
Apr. 2005
Aug. 2005
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.4 / Aug. 2005
1
Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L/S)T(P) Series
DESCRIPTION
The Hynix HY57V281620E(L/S)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the mem-
ory applications which require wide data I/O and high bandwidth. HY57V281620E(L/S)T(P) series is organized as
4banks of 2,097,152 x 16.
HY57V281620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
Voltage: VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
54 Pin TSOPII (Lead or Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
•
•
•
•
Data mask function by UDQM, LDQM
•
Internal four banks operation
•
Auto refresh and self refresh
- Commercial Temperature (0
o
C to 70
o
C)
Operating Temperature
Burst Read Single Write operation
•
•
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HY57V281620E(L/S)T(P)-5
HY57V281620E(L/S)T(P)-6
HY57V281620E(L/S)T(P)-7
HY57V281620E(L/S)T(P)-H
Note:
1. HY57V281620ET Series: Normal power, Leaded.
2. HY57V281620ELT Series: Low power, Leaded.
3. HY57V281620EST Series: Super Low power, Leaded.
4. HY57V281620ETP Series: Normal power, Lead Free.
5. HY57V281620ELTP Series: Low power, Lead Free.
6. HY57V281620ELTP Series: Super Low power, Lead Free.
7. HY57V281620EST(P) Series: Super Low power; Contact Hynix for availability
8. HY57V281620E(L/S)T(P)-x: Commercial Temperature (0
o
C to 70
o
C)
9. HY57V281620E(L/S)T(P)-xI: Industrial Temperature (-40
o
C to 85
o
C)
Rev. 1.4 / Aug. 2005
Clock Frequency
200MHz
166MHz
143MHz
133MHz
Organization
Interface
Package
4Banks x 2Mbits x16
LVTTL
54 Pin TSOPII
2
Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L/S)T(P) Series
PIN DESCRIPTION
SYMBOL
CLK
TYPE
Clock
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A11
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
NC
Data Output Power/Ground Power supply for output buffers
No Connection
No connection
Rev. 1.4 / Aug. 2005
4
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