The AS7C181026LL is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 65,536 words × 16
bits. It is designed for portable applications where fast data access, long battery life, low heat dissipation, and simple interfacing are desired.
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Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55*/70/100 ns are ideal for high performance applications. The chip enable input CE
permits easy memory expansion with multiple-bank memory systems.
When CE is High, or when UB and LB are simultaneously pulled Low, the device enters standby mode. The AS7C181026LL is guaranteed not
to exceed 2.0 µW power consumption in CMOS standby mode. This device also offers data retention down to 1.5V.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
The device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the
smallest possible footprint. This 48-ball JEDEC registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm.
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In the AS7C181026LL design, priority was placed on low power, while maintaining moderately high performance. To reduce standby and
data retention current, a 6-transistor memory cell was utilized. Active power was reduced considerably over traditional designs by using
Intelliwatt™ power reduction circuitry. With Intelliwatt™, SRAM powers down unused circuits between access operations, providing
incremental power savings. During periods of inactivity, Intelliwatt™ SRAM power consumption approaches fully deactivated standby
power, even though the chip is enabled. This power savings, both in active and inactive modes, results in longer battery life, and better
system marketability. All chip inputs and outputs are TTL-compatible, and operation is from a single power supply.
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Parameter
Voltage on any input pin relative to
V
SS
Voltabe on any I/O pin
Power dissipation
Storage temperature (plastic)
DC output current
Symbol
V
tIN
V
tI/O
P
D
T
stg
I
out
Min
–1
–1
–
–55
–
Max
+2.5
V
DD
+ 0.5
1.0
+150
20
Unit
V
V
W
o
C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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CE
H
L
L
L
L
L
L
L
X
WE
X
H
H
H
L
L
L
X
X
OE
X
L
L
L
X
X
X
H
X
LB
X
L
H
L
L
L
H
X
H
UB
X
H
L
L
L
H
L
X
H
I/O0–I/O7
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
High Z
High Z
High Z
I/O8–I/O15
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
D
IN
High Z
High Z
Mode
Standby, power down
Read I/O0–I/O7
Read I/O8–I/O15
Read I/O0–I/O15
Write I/O0–I/O15
Write I/O0–I/O7
Write I/O8–I/O15
Output disable
Disable, power down
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Key: X = don’t care, L = Low, H = High
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Parameter
Supply voltage
Input voltage
Ambient operating temperature
†
Symbol
V
DD
V
SS
V
IH
V
IL
Commercial
Industrial
T
A
T
A
Min
1.65
0.0
0.7 × V
DD
–0.5
†
0
-40
Typ
1.80
0.0
–
–
–
–
Max
1.95
0.0
V
DD
+ 0.5
0.3 × V
DD
70
85
Unit
V
V
V
V
°C
°C
V
IL
min = –3.0V for pulse width less than 10 ns.
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-55*
Parameter
Input leakage
current
Symbol
|
I
LI
|
Test conditions
0V
≤
V
in
≤
V
DD
Outputs disabled,
0V
≤
V
out
≤
V
DD
CE
≤
V
IL
, V
DD
= Max,
f = f
Max
= 1/t
RC,
I
OUT
= 0
CE
=
V
SS
, V
DD
= Max, f = 0,
I
OUT
= 0
CE
≥
V
IH
, V
DD
= Max,
f = f
Max
= 1/t
RC
CE
≥
V
DD
–0.2V, V
DD
=
Max,
V
in
≤
V
SS
+ 0.2V or
V
in
≥
V
DD
- 0.2V, f = 0
I
OL
= 100 µA, V
DD
= Min
I
OH
= –100 µA, V
DD
= Min
–
Min
–
–
–
Max
1
1
19
20
20
–
Min
–
–
–
-70
Max
1
1
15
20
20
–
-100
Min
–
–
–
Max
1
1
10
20
20
Unit
µA
µA
mA
µA
µA
Output leakage
|
I
LO
|
current
Operating
power supply
current
I
DD
I
DD1
I
SB
I
SB1
V
OL
V
OH
Standby
power supply
current
–
–
0.8×V
DD
1
0.2
–
–
–
0.8×V
DD
1
0.2
–
–
–
0.8×V
DD
1
0.2
–
µA
Output voltage
V
*For availability of 55 ns device, contact Alliance.
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Parameter
Input capacitance
I/O capacitance
Outputs disabled in all cases.
I
CC
= worst case power consumption.
I
SB
= current for the disabled, bus-active condition.
I
CC1
= enabled, bus-inactive condition.
I
SB1
= “full standby” or the disabled, bus-inactive condition.
I
CCDR
= current in data retention (reduced VDD) mode.
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9
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE, LB, UB
I/O
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Max Unit
5
7
pF
pF
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3
55*
Parameter
Read cycle time
Address access time
Chip enable access time
Output enable (OE) access time
Output hold from address change
Chip enable Low to output in Low Z
Chip enable High to output in High Z
OE Low to output in Low Z
OE High to output in High Z
Byte select access time
Byte select Low to Low-Z
Byte select High to High-Z
Power up time
Power down time
*For availability of 55 ns device, contact Alliance.
70
Max
–
55
55
25
–
–
25
–
25
25
–
25
–
55
Min
70
–
–
–
3
3
–
3
–
–
3
–
0
–
Max
–
70
70
35
–
–
35
–
35
35
–
35
–
70
Min
100
–
–
–
3
3
–
3
–
–
3
–
0
–
100
Max
–
100
100
50
–
–
50
–
50
50
–
50
–
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,5
4,5
4, 5, 12
4, 5, 12
5
4, 5, 12
4, 5, 12
4, 5
4, 5
3
3, 12
Notes
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
BA
t
BLZ
t
BHZ
t
PU
t
PD
Min
55
–
–
–
3
3
–
3
–
–
3
–
0
–
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Rising input
Falling input
Undefined output/don’t care
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6,7,9
Address
Data out
t
OH
Previous data valid
t
AA
t
RC
t
OH
Data valid
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6,8,9
t
RC
Address
t
AA
OE
t
OLZ
CE
t
LZ
LB, UB
t
BLZ
Data out
t
BA
Data valid
t
BHZ
t
ACE
t
OHZ
t
HZ
t
OE
t
OH
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55*
Parameter
Write cycle time
Chip enable to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in High Z
Output active from write end
Byte Select low to end of write
*For availability of 55 ns device, contact Alliance.
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