DISCRETE SEMICONDUCTORS
DATA SHEET
BSN205; BSN205A
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a TO-92
variant envelope. Designed primarily
as a line current interrupter in
telephone sets, it can also be applied
in other applications such as in relays,
line and high speed transformer
drivers etc.
FEATURES
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching
•
No secondary breakdown
•
Low R
DS(on)
PINNING - TO-92 VARIANT
BSN205
1
2
3
PIN CONFIGURATION
= gate
= drain
= source
1
2
3
QUICK REFERENCE DATA
Drain-source voltage
Gate-source voltage (open drain)
Drain current (DC)
Total power dissipation up to
T
amb
= 25
°C
Drain-source ON-resistance
I
D
= 400 mA; V
GS
= 10 V
Transfer admittance
I
D
= 400 mA; V
DS
= 25 V
P
tot
BSN205; BSN205A
V
DS
±
V
GSO
I
D
max.
max.
max.
max.
typ.
max.
200 V
20 V
300 mA
1 W
4.5
Ω
6
Ω
200 mS
350 mS
R
DS(on)
Y
fs
min.
typ.
BSN205A
= source
= gate
= drain
handbook, halfpage
d
1
2
3
g
s
MAM148
Note:
various pinout configurations available.
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
Gate-source voltage (open drain)
Drain current (DC)
Drain current (peak)
Total power dissipation up to T
amb
= 25
°C
(note 1)
Storage temperature range
Junction temperature
THERMAL RESISTANCE
From junction to ambient (note 1)
Note
R
th j-a
V
DS
BSN205; BSN205A
max.
max.
max.
max.
max.
max.
200 V
20 V
300 mA
1.2 A
1 W
150
°C
±
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
−65
to
+
150
°C
=
125 K/W
1. Transistor mounted on printed-circuit board, max. lead length 4 mm, mounting pad for drain lead
min. 10 mm
×
10 mm.
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified
Drain-source breakdown voltage
I
D
= 10
µA;
V
GS
= 0
Drain-source leakage current
V
DS
= 160 V; V
GS
= 0
Gate-source leakage current
V
GS
= 20 V; V
DS
= 0
Gate threshold voltage
I
D
= 1 mA; V
DS
= V
GS
Drain-source ON-resistance
I
D
= 400 mA; V
GS
= 10 V
Transfer admittance
I
D
= 400 mA; V
DS
= 25 V
Input capacitance at f = 1 MHz
V
DS
= 25 V; V
GS
= 0
C
iss
typ.
max.
45 pF
60 pF
| Y
fs
|
min.
typ.
200 mS
350 mS
R
DS(on)
typ.
max.
V
GS(th)
min.
max.
0.8 V
2.8 V
4
Ω
6
Ω
I
GSS
max.
100 nA
I
DSS
max.
1
µA
V
(BR) DSS
min.
200 V
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
Output capacitance at f = 1 MHz
V
DS
= 25 V; V
GS
= 0
Feedback capacitance at f = 1 MHz
V
DS
= 25 V; V
GS
= 0
Switching times (see Figs 2 and 3)
I
D
= 250 mA; V
DD
= 50 V
V
GS
= 0 to 10 V
t
on
C
rss
C
oss
BSN205; BSN205A
typ.
max.
15 pF
25 pF
typ.
max.
3.5 pF
10 pF
typ.
max.
typ.
max.
5 ns
10 ns
15 ns
20 ns
t
off
handbook, halfpage
VDD = 50 V
handbook, halfpage
90 %
INPUT
10 %
90 %
10 V
0V
ID
50
Ω
MBB691
OUTPUT
10 %
ton
toff
MBB692
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PACKAGE OUTLINES
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
BSN205; BSN205A
SOT54 variant
c
L2
E
d
A
L
b
1
2
D
e1
e
3
b
1
L1
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
5.2
5.0
b
0.48
0.40
b1
0.66
0.56
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
e
2.54
e1
1.27
L
14.5
12.7
L1
(1)
max
2.5
L2
max
2.5
Notes
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54 variant
REFERENCES
IEC
JEDEC
TO-92
EIAJ
SC-43
EUROPEAN
PROJECTION
ISSUE DATE
97-04-14
April 1995
5
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