DISCRETE SEMICONDUCTORS
DATA SHEET
BSN274; BSN274A
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL,
etc., due to low threshold voltage
•
High speed switching
•
No secondary breakdown
DESCRIPTION
Silicon n-channel enhancement
mode vertical D-MOS transistor in
TO-92 variant envelope and intended
for use as a line current interruptor in
telephone sets and for applications in
relay, high speed and line transformer
drivers.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
R
DS(on)
V
GS(th)
PARAMETER
drain-source voltage
drain current (DC)
drain-source on-resistance
threshold voltage
BSN274; BSN274A
MAX.
270
250
8
2
V
UNIT
mA
Ω
V
PINNING
(BSN274)
PIN
1
2
3
gate
drain
source
DESCRIPTION
PINNING
(BSN274A)
PIN
1
2
3
gate
drain
DESCRIPTION
source
Note: Other pinnings are available on request.
PIN CONFIGURATION - TO-92 VARIANT
handbook, halfpage
d
1
2
3
g
MAM146
s
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
±V
GSO
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
drain-source voltage
gate-source voltage
drain current
drain current
total power dissipation
storage temperature range
operating junction temperature
open drain
DC
peak
up to T
amb
= 25
°C
(note 1)
CONDITIONS
BSN274; BSN274A
MIN.
−
−
−
−
−
−65
−
MAX.
270
20
250
1
1
150
150
V
V
UNIT
mA
A
W
°C
°C
THERMAL RESISTANCE
SYMBOL
R
th j-a
Notes
1. Transistor mounted on printed circuit board, maximum lead length 4 mm, mounting pad for drain leads minimum
10 mm
×
10 mm.
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
I
DSS
±I
GSS
V
GS(th)
R
DS(on)
R
DS(on)
Y
fs
C
iss
PARAMETER
drain-source breakdown voltage
drain-source leakage current
gate-source leakage current
gate threshold voltage
drain-source on-resistance
drain-source on-resistance
transfer admittance
input capacitance
CONDITIONS
V
GS
= 0
I
D
= 10
µA
V
DS
= 220 V
V
GS
= 0
±V
GS
= 20 V
V
DS
= 0
I
D
= 1 mA
V
DS
= V
GS
I
D
= 250 mA
V
GS
= 10 V
I
D
= 20 mA
V
GS
= 2.4 V
I
D
= 250 mA
V
DS
= 25 V
V
DS
= 25 V
V
GS
= 0
f = 1 MHz
V
DS
= 25 V
V
GS
= 0
f = 1 MHz
MIN.
270
−
−
0.8
−
−
200
−
−
−
−
−
6.5
9
400
65
TYP.
−
1
100
2
8
14
−
90
MAX.
UNIT
V
µA
nA
V
Ω
Ω
mS
pF
PARAMETER
from junction to ambient (note 1)
VALUE
125
UNIT
K/W
C
oss
output capacitance
−
20
30
pF
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
SYMBOL
C
rss
PARAMETER
feedback capacitance
CONDITIONS
V
DS
= 25 V
V
GS
= 0
f = 1 MHz
I
D
= 250 mA
V
DD
= 50 V
V
GS
= 0 to 10 V
I
D
= 250 mA
V
DD
= 50 V
V
GS
= 0 to 10 V
−
MIN.
5
BSN274; BSN274A
TYP.
15
MAX.
UNIT
pF
Switching times (see Figs
2
and
3)
t
on
switching-on time
−
5
10
ns
t
off
switching-off time
−
20
30
ns
handbook, halfpage
VDD = 50 V
handbook, halfpage
90 %
INPUT
10 %
90 %
10 V
0V
ID
50
Ω
MSA631
OUTPUT
10 %
ton
toff
MBB692
Fig.2 Switching time test circuit.
Fig.3 Input and output waveforms.
April 1995
4
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
PACKAGE OUTLINES
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
BSN274; BSN274A
SOT54 variant
c
L2
E
d
A
L
b
1
2
D
e1
e
3
b
1
L1
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
5.2
5.0
b
0.48
0.40
b1
0.66
0.56
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
e
2.54
e1
1.27
L
14.5
12.7
L1
(1)
max
2.5
L2
max
2.5
Notes
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54 variant
REFERENCES
IEC
JEDEC
TO-92
EIAJ
SC-43
EUROPEAN
PROJECTION
ISSUE DATE
97-04-14
April 1995
5
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