Resolution varies with PWM switching frequency (13 MHz Clock in Double Update mode), 50.7 kHz = 9 bits, 6.3 kHz = 12 bits.
Specifications subject to change without notice.
–2–
REV. B
ADMC331
TIMING PARAMETERS
Parameter
Clock Signals
t
CK
is defined as 0.5 t
CKI
. The ADMC331 uses an input clock with a frequency equal
to half the instruction rate; a 13 MHz input clock (which is equivalent to 76.9 ns)
yields a 38.5 ns processor cycle (equivalent to 26 MHz). t
CK
values within the range
of 0.5 t
CKI
period should be substituted for all relevant timing parameters to obtain
specification value.
Example: t
CKH
= 0.5 t
CK
– 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements:
t
CKI
CLKIN Period
t
CKIL
CLKIN Width Low
CLKIN Width High
t
CKIH
Switching Characteristics:
t
CKL
CLKOUT Width Low
t
CKH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
t
RSP
RESET Width Low
5 t
CK1
ns
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
PWMTRIP
Width Low
2 t
CK
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Min
Max
Unit
76.9
20
20
0.5 t
CK
– 10
0.5 t
CK
– 10
0
150
ns
ns
ns
ns
ns
ns
20
t
CKI
t
CKIH
CLKIN
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
Figure 1. Clock Signals
REV. B
–3–
ADMC331
Parameter
Serial Ports
Timing Requirements:
t
SCK
SCLK Period
DR/TFS/RFS Setup before SCLK Low
t
SCS
t
SCH
DR/TFS/RFS Hold after SCLK Low
t
SCP
SCLK
IN
Width
Switching Characteristics:
t
CC
CLKOUT High to SCLK
OUT
t
SCDE
SCLK High to DT Enable
t
SCDV
SCLK High to DT Valid
TFS/RFS
OUT
Hold after SCLK High
t
RH
t
RD
TFS/RFS
OUT
Delay from SCLK High
t
SCDH
DT Hold after SCLK High
SCLK High to DT Disable
t
SCDD
t
TDE
TFS (Alt) to DT Enable
t
TDV
TFS (Alt) to DT Valid
t
RDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
Min
Max
Unit
100
15
20
40
0.25 t
CK
0
0
30
0
30
0
25
30
0.25 t
CK
+ 20
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
t
CC
t
CC
t
SCK
SCLK
t
SCS
DR
RFS
IN
TFS
IN
t
SCH
t
SCP
t
SCP
t
RD
t
RH
RFS
OUT
TFS
OUT
t
SCDV
t
SCDE
DT
t
SCDD
t
SCDH
t
TDE
t
TDV
TFS
(ALTERNATE
FRAME MODE)
t
RDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
Figure 2. Serial Ports
–4–
REV. B
ADMC331
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Supply Voltage (AV
DD
) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range (Ambient) . . . – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
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