®
®
A SUBSIDIARY OF C&D TECHNOLOGIES
Single Output
LEN D12 Models
Non Isolated, 12V
IN
, 0.8-5V
OUT
28 Amp DC/DC Converters
Features
■
■
Eighth brick, through hole or SMT
2-phase buck regulators for new
distributed 12V power architectures
12V input (10.2-13.8V range)
0.8-2.5V
OUT,
3.3V
OUT
@ 28A, 5V
OUT
@ 25A
Non-isolated, fixed-frequency,
synchronous-rectifier topology
Efficiencies to 95% @ 25 Amps
Noise as low as 25mVp-p
Stable no-load operation
On/Off control, trim & sense functions
Output Overvoltage Protection
Input Over/Undervoltage lockout
Thermal shutdown
Designed to meet UL/EN/IEC60950
EMC compliant
■
■
■
■
■
■
■
■
■
■
■
■
The LEN D12 Series of non-isolated eighth bricks are ideal building blocks for
emerging, on-board power-distribution schemes in which isolated 12V buses deliver
power to any number of non-isolated, step-down buck regulators. LEN D12 DC/DC's
accept a 12V input (10.2V to 13.8V input range) and convert it, with the highest
efficiency in the smallest space, to a 0.8, 1, 1.2, 1.5, 1.8, 2, 2.5, or 3.3 Volt output
fully rated at 28 Amps, or 5 Volt output at 25 Amps.
LEN D12's are ideal POLPP's (point-of-use/load power processors) and they
typically require no external components. They occupy the standard eighth-brick
board space (0.9" x 2.3") and come in either through-hole packages or surface-
mount packages with a profile of only 0.46" (0.5" including optional heat sink).
The LEN's best-in-class power density is achieved with a fully synchronous,
fixed-frequency, 2-phase buck topology that delivers extremely high efficiency (95%
for 5V
OUT
models), low noise (25mVp-p typ.), tight line/load regulation (±0.25%
max.), quick step response (150µsec), stable no-load operation, and no output
reverse conduction.
The fully functional LEN's feature input over/undervoltage lockout, output over-
voltage and overcurrent detection, continuous short-circuit protection, overtempera-
ture protection, an output-voltage trim function, a remote on/off control pin, and a
sense pin. High efficiency enables the LEN D12's to deliver rated output currents of
25 Amps at ambient temperatures to +65°C with 200 lfm air flow without heat sink.
If your new system boards call for multiple supply voltages, check out the
economics of on-board 12V distributed power. If you don't need to pay for multiple
isolation barriers, DATEL's non-isolated ¼ and
1
/
8
brick's will save you money.
+INPUT
(5)
+OUTPUT
(7,9)
➀
+SENSE
(10)
COMMON
(1)
CURRENT
SENSE
V
CC
ON/OFF
CONTROL
(4)
COMMON
(6, 8)
2-PHASE
PWM
CONTROLLER
REFERENCE &
ERROR AMP
V
OUT
TRIM
(2)
➀
Only one phase of two shown.
Figure 1. Simplified Schematic
DATEL, Inc., Mansfield, MA 02048 (USA) · Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 · Email: sales@datel.com · Internet: www.datel.com
LEN D12 Models
N O N - I S O L AT E D , 2 8 A E I G H T H B R I C K , D C / D C C O N V E R T E R S
Performance Specifications and Ordering Guide
Output
Model
LEN-0.8/28-D12
LEN-1/28-D12
LEN-1.2/28-D12
LEN-1.5/28-D12
LEN-1.8/28-D12
LEN-2/28-D12
LEN-2.5/28-D12
LEN-3.3/28-D12
LEN-5/25-D12
➀
Input
Regulation (Max.)
➂
Line
Load
±0.25%
±0.25%
±0.25%
±0.25%
±0.2%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
V
OUT
(Volts)
0.8
1
1.2
1.5
1.8
2
2.5
3.3
5
I
OUT
(Amps)
28
28
28
28
28
28
28
28
25
R/N (mVp-p)
➁
Typ.
Max.
30
30
30
20
20
20
20
30
30
50
50
50
50
50
50
50
50
50
V
IN
Nom. Range
➄
(Volts)
(Volts)
12
12
12
12
12
12
12
12
12
10.2-13.8
10.2-13.8
10.2-13.8
10.2-13.8
10.2-13.8
10.2-13.8
10.2-13.8
10.2-13.8
10.2-13.8
I
IN
➃
(mA/A)
80/2.3
80/2.8
83/3.3
89/4
92/4.7
100/5.2
130/6.4
130/7.4
130/11
Efficiency
Full Load
½ Load
Min.
79%
80%
83%
85%
89%
88%
89%
91%
92%
Typ.
80%
82.5%
86.5%
88%
90%
90%
91%
93%
95%
Typ.
84.5%
86%
88%
90%
91%
91.5%
93%
94%
95.5%
Package
(Case,
Pinout)
C43,C44, P62
C43,C44, P62
C43,C44, P62
C43,C44, P62
C43,C44, P62
C43,C44, P62
C43,C44, P62
C43,C44, P62
C43,C44, P62
➃
Nominal line voltage, no-load/full-load conditions.
➀
Typical at T
A
= +25°C under nominal line voltage and full-load conditions, unless otherwise
noted. All models are tested and specified with external 33µF capacitor installed across their
➄
The operating input voltage is 10.2V to 13.8V. However, 10.8V
IN
is required for the DC/DC
to properly start up under all line, load and temperature conditions. The 10.8V potential must be
input and output pins.
maintained across the inputs until the output is up and regulating. After the output is regulating,
➁
Ripple/Noise (R/N) is tested/specified over a 20MHz bandwidth.
the operating input range is 10.2V to 13.8V.
➂
These devices have no minimum-load requirements and will regulate under no-load conditions.
Regulation specifications describe the output-voltage deviation as the line voltage or load is
varied from its nominal/midpoint value to either extreme.
P A R T
N U M B E R
S T R U C T U R E
M E C H A N I C A L
S P E C I F I C A T I O N S
L EN
-
1.8
/
28
-
D12 M H
Output
Configuration:
L
= Unipolar
Low Voltage
Non-Isolated Eighth Brick
Nominal Output Voltage:
0.8, 1, 1.2, 1.5, 1.8, 2, 2.5, 3.3
or 5 Volts
Heat Sink option
Surface-Mount Package
Blank
= Through-hole
package
Input Voltage Range:
D12
= 10.2 to 13.8 Volts
(12V nominal)
Maximum Rated Output
Current in Amps
0.50 (12.7)
W/ HEATSINK
0.46 (11.68)
WO/ HEATSINK
Case C43
2.30 (58.42)
2.23 (56.64)
SMT LEADS COPLANAR
TO 0.004 (0.10)
0.150
(3.81)
0.125
(3.18)
1
6
7
8
9
10
0.035
(0.89)
Note:
Not all model number combinations
are available. Contact DATEL.
0.600
(15.24)
2
3
4
5
0.90
(22.86)
0.150 TYP.
(3.81)
BOTTOM VIEW
DIMENSIONS ARE IN INCHES (MM)
0.110
(2.79)
0.50 (12.7)
W/ HEATSINK
0.46 (11.68)
WO/ HEATSINK
Case C44
2.23 (56.64)
A
Pin
1
2
3
4
5
I/O Connections
Function P62
Pin
Function P62
Common
6
Common
V
OUT
Trim
7
+Output
NC
8
Common
On/Off control
9
+Output
+Input
10
+Sense
0.200 MIN.
(5.08)
0.122
(3.10)
PLASTIC STANDOFFS
ARE RELIEVED 0.030 (0.76)
IN SOLDER JOINT AREA
PINS 2-4, 10:
0.040 ±0.001
(1.016 ±0.025)
PINS 1, 5-9:
0.062 ±0.001
(1.575 ±0.025)
2.00 (50.80)
B
A
B
1
2
3
4
5
0.600 (15.24)
4 EQ. SP. @ 0.150 (3.81)
6
7
8
9
10
BOTTOM VIEW
0.90
(22.86)
2
N O N - I S O L AT E D , 2 8 A E I G H T H B R I C K , D C / D C C O N V E R T E R S
LEN D12 Models
Performance/Functional Specifications
Typical @ T
A
= +25°C under nominal line voltage and full-load conditions unless noted.
➀
Absolute Maximum Ratings
Input Voltage:
Continuous or transient
On/Off Control
(Pin 11)
Input Reverse-Polarity Protection
Output Overvoltage Protection
Output Current
15.5 Volts
+V
IN
None
V
OUT
+20%
Current limited. Devices can
withstand sustained output short
circuits without damage.
–55½ to +125°C
+300°C
Input
Input Voltage Range
Input Current:
Normal Operating Conditions
Inrush Transient
Standby/Off Mode
Output Short-Circuit Condition
➁
Input Reflected Ripple Current
➁
Input Filter Type
Overvoltage Protection
Reverse-Polarity Protection
Undervoltage Shutdown
On/Off Control
➂
10.2-13.8 Volts (12V nominal)
➅
See Ordering Guide
TBD
3.5mA
130mA
20mAp-p
Capacitive (66µF)
14.3 Volts
None
9.4 Volts
On = open or 0 to +0.4V
Off = +2.8V to +V
IN
(<3mA)
Storage Temperature
Lead Temperature
(soldering, 10 sec.)
These are stress ratings. Exposure of devices to any of these conditions may adversely
affect long-term reliability. Proper operation under conditions other than those listed in the
Performance/Functional Specifications Table is not implied.
Output
V
OUT
Accuracy
(50% load)
Minimum Loading
➀
Maximum Capacitive Load
V
OUT
Trim Range
➁
±1.5% maximum
No load
10,000µF (low ESR, OSCON)
±10% for V
OUT
=
≥1.8V
+10%/–3% for V
OUT
1.5V and lower
(no trim for 0.8V models)
See Ordering Guide
3% over line/load temperature
See Ordering Guide
T E C H N I C A L
N O T E S
Return Current Paths
The LEN D12 are non-isolated DC/DC converters. Their Common pins (pins
1, 6 and 8) are connected to each other internally (see Figure 1). To the
extent possible (with the intent of minimizing ground loops), input return
current should be directed through pin 1 (also referred to as –Input or
Input Return), and output return current should be directed through pin 6
and 8 (also referred to as –Output or Output Return). Any on/off control
signals applied to pin 4 (On/Off Control) should be referenced to Common
(specifically pin 1).
I/O Filtering and Noise Reduction
All models in the LEN D12 Series are tested and specified with external
33µF tantalum input and output capacitors. These capacitors are necessary
to accommodate our test equipment and may not be required to achieve
desired performance in your application. The LEN D12's are designed with
high-quality, high-performance
internal
I/O caps, and will operate within spec
in most applications with
no additional external components.
In particular, the LEN D12's input capacitors are specified for low ESR
and are fully rated to handle the units' input ripple currents. Similarly, the
internal output capacitors are specified for low ESR and full-range frequency
response. As shown in the Performance Curves, removal of the external
33µF tantalum output caps has minimal effect on output noise.
In critical applications, input/output ripple/noise may be further reduced using
filtering techniques, the simplest being the installation of external I/O caps.
External input capacitors serve primarily as energy-storage devices. They
minimize high-frequency variations in input voltage (usually caused by IR
drops in conductors leading to the DC/DC) as the switching converter draws
pulses of current. Input capacitors should be selected for bulk capacitance (at
appropriate frequencies), low ESR, and high rms-ripple-current ratings. The
switching nature of modern DC/DC's requires that the dc input voltage source
have low ac impedance and the frequencies of interest. Highly inductive
source impedances can greatly affect system stability. Your specific system
configuration may necessitate additional considerations.
Output ripple/noise (also referred to as periodic and random deviations
or PARD) may be reduced below specified limits with the installation of
additional external output capacitors. Output capacitors function as true filter
Ripple/Noise
(20MHz BW)
➀ ➁ ➃
Total Accuracy
Efficiency
➁
Overcurrent Detection and Short-Circuit Protection:
➁
Current-Limiting Detection Point
35 Amps
Short-Circuit Detection Point
98% of V
OUT
set
SC Protection Technique
Hiccup with auto recovery
Short-Circuit Current
TBD
Dynamic Characteristics
Transient Response
(25% load step)
Start-Up Time:
➁
V
IN
to V
OUT
and On/Off to V
OUT
Switching Frequency
Calculated MTBF
➄
Operating Temperature:
(Ambient)
➁
Without Derating (With 200 lfm)
With Derating
Thermal Shutdown
Dimensions
Pin Material
Weight
Flamability Rating
100µsec to ±2% of final value
20ms
320kHz ±40kHz
Environmental
TBD million hours
–40 to +65°C (model dependent)
See Derating Curves
+125°C
Physical
See Mechanical Dimensions
Copper, solder coated over nickel underplate
0.6 ounces (17g)
UL94V-0
➀
All models are tested and specified with external 33µF tantalum input and output capacitors.
These capacitors are necessary to accommodate our test equipment and may not be
required to achieve specified performance in your applications. All models are stable and
regulate within spec under no-load conditions.
➁
Input Ripple Current is tested/specified over a 5-20MHz bandwidth with an external 33µF
input capacitor and a simulated source impedance of 220µF and 12µH. See I/O Filtering,
Input Ripple Current and Output Noise for details.
➂
The On/Off Control (pin 4) is designed to be driven with open-collector logic or the appli-
cation of appropriate voltages (referenced to Common, pins 1, 6 and 8).
➃
Output noise may be further reduced with the installation of additional external output
filtering. See I/O Filtering and Noise Reduction.
➄
MTBF’s are calculated using Telcordia SR-332(Bellcore), ground fixed, T
A
= +25°C, full
power, natural convection, TBD pcb temperature.
➅
See Performance Specifications, note 6.
3
LEN D12 Models
N O N - I S O L AT E D , 2 8 A E I G H T H B R I C K , D C / D C C O N V E R T E R S
elements and should be selected for bulk capacitance, low ESR, and appro-
priate frequency response. Any scope measurements of PARD should be
made directly at the DC/DC output pins with scope probe ground less than
0.5" in length.
All external capacitors should have appropriate voltage ratings and be located
as close to the converters as possible. Temperature variations for all relevant
parameters should be taken into consideration.
The most effective combination of external I/O capacitors will be a function
of your line voltage and source impedance, as well as your particular load and
layout conditions. Our Applications Engineers can recommend potential solu-
tions and discuss the possibility of our modifying a given device’s internal filter-
ing to meet your specific requirements. Contact our Applications Engineering
Group for additional details.
Input Fusing
Most applications and or safety agencies require the installation of fuses
at the inputs of power conversion components. LEN D12 Series DC/DC
converters are not internally fused. Therefore, input fusing is mandatory for
safety reasons, and safety agencies require a time delay fuse with a value
no greater than 40Amps, which should be installed within the ungrounded
input path to the converter.
As a rule of thumb however, we recommend to use a normal-blow or slow-
blow fuse with a typical value of about twice the maximum input current,
calculated at low line with the converters minimum efficiency.
Safety Considerations
LEN D12's are non-isolated DC/DC converters. In general, all DC/DC's
must be installed, including considerations for I/O voltages and spacing/
separation requirements, in compliance with relevant safety-agency speci-
fications (usually UL/IEC/EN60950).
In particular, for a non-isolated converter's output voltage to meet SELV
(safety extra low voltage) requirements, its input must be SELV compliant.
If the output needs to be ELV (extra low voltage), the input must be ELV.
Start-Up Time
The V
IN
to V
OUT
Start-Up Time is the interval between the time at which a
ramping input voltage crosses the lower limit of the specified input voltage
range (10.2 Volts) and the fully loaded output voltage enters and remains
within its specified accuracy band. Actual measured times will vary with input
source impedance, external input capacitance, and the slew rate and final
value of the input voltage as it appears to the converter.
The On/Off to V
OUT
Start-Up Time assumes the converter is turned off via the
On/Off Control with the nominal input voltage already applied to the converter.
The specification defines the interval between the time at which the converter
is turned on and the fully loaded output voltage enters and remains within its
specified accuracy band. See Typical Performance Curves.
Remote Sense
LEN D12 Series DC/DC converters offer an output sense function on pin 10.
The sense function enables point-of-use regulation for overcoming moderate
IR drops in conductors and/or cabling. Since these are non-isolated devices
whose inputs and outputs usually share the same ground plane, sense is
provided only for the +Output.
The remote sense line is part of the feedback control loop regulating the
DC/DC converter’s output. The sense line carries very little current and
consequently requires a minimal cross-sectional-area conductor. As such,
it is not a low-impedance point and must be treated with care in layout and
cabling. Sense lines should be run adjacent to signals (preferably ground),
and in cable and/or discrete-wiring applications, twisted-pair or similar
techniques should be used. To prevent high frequency voltage differences
between V
OUT
and Sense, we recommend installation of a 1000pF capacitor
close to the converter.
The sense function is capable of compensating for voltage drops between the
+Output and +Sense pins that do not exceed 10% of V
OUT
.
[V
OUT
(+) – Common] – [Sense(+) – Common]
≤
10%V
OUT
Power derating (output current limiting) is based upon maximum output
current and voltage at the converter's output pins. Use of trim and sense
functions can cause the output voltage to increase, thereby increasing output
power beyond the converter's specified rating. Therefore:
(V
OUT
at pins) x (I
OUT
)
≤
rated output power
The internal 10.5Ω resistor between +Sense and +Output (see Figure 1)
serves to protect the sense function by limiting the output current flowing
through the sense line if the main output is disconnected. It also prevents
output voltage runaway if the sense connection is disconnected.
Note: If devices have the +Sense pin (pin 10) installed (no part-number
suffix) and the sense function is not used for remote regulation, +Sense
(pin 10) must be tied to +Output (pin 7, 9) at the DC/DC converter pins.
On/Off Control
The On/Off Control pin may be used for remote on/off operation. LEN D12
Series DC/DC converters are designed so that they are enabled when the
control pin is left open (or pulled low to 0 to +0.4V) and disabled when the
control pin is pulled high (+2.8V to +V
IN
). As shown in Figure 2, all models
have an internal 20kΩ pull-down resistor to Common (ground).
Dynamic control of the on/off function is best accomplished with a mechanical
relay or open-collector/open-drain drive circuit (optically isolated if appropri-
ate). The drive circuit should be able to sink appropriate current when
activated and withstand appropriate voltage when deactivated.
½½½½½½
½½½½
½½½½½½½½
½½½½½½
½½½½
½½½½½½
½½½½½½½
½
½
½½½½
½½½½½
½½½½½½
½½½½½½½½½½
½½½½½½
ON/OFF pin open: Logic Low = DC/DC converter On
ON/OFF pin >2.8V: Logic High = DC/DC converter Off
Figure 2. Driving the On/Off Control Pin
The on/off control can be driven using a circuit comparable to that shown in
Figure 2. Leaving the On/Off control pin open or applying a voltage between
0V and +0.4V will turn on the converter. Applied voltages between +2.8V and
+V
IN
will disable the converter.
4
N O N - I S O L AT E D , 2 8 A E I G H T H B R I C K , D C / D C C O N V E R T E R S
LEN D12 Models
Power-up sequencing
If a controlled start-up of one or more LEN D12 Series DC/DC converters
is required, or if several output voltages need to be powered-up in a given
sequence, the On/Off control pin can be pulled high to +V
IN
with an external
5.6kΩ restistor. While input voltage and/or other converters are ramping up,
the control pin is pulled high and the converter remains disabled. To enable
the output voltage, the control pin needs to be pulled low in the configuration
shown in Figure 3.
+INPUT
which can then be connected, as shown in Figure 5, between the Trim pin
and +Output to trim down the output voltage, or between the Trim pin and
Common to trim up the output voltage. Fixed resistors should have absolute
TCR’s less than 100ppm/°C to ensure stability.
The equations below can be used as starting points for selecting specific trim-
resistor values. Recall, untrimmed devices are guaranteed to be
±1%
accurate.
Adjustment beyond the specified adjustment range is not recommended.
½½½½½½½
2.5V
½½½½½½
5.6kΩ
ON/OFF
CONTROL
+
–
20kΩ
½½½½
½½½½½½
½½½½½½
½½½½
½½½½
½½½½½
½½½½
COMMON
Figure 4. Trim Connections Using a Trimpot
External Input Open: On/Off pin High = DC/DC converter Off
External Input Low: On/Off pin Low = DC/DC converter On
Figure 3. Driving The Power-Up With An External Pull-up Resistor
½½½½½½
½½½½½½½
½½½½ ½
½½½½
½½½½
½½½½½½
½½½½½½
½½½½½ ½
½½
½½½½
Output Overvoltage Protection
The LEN D12 Series output voltage is monitored. If the output voltage rises
to a level, which could be damaging to the load, the internal sensing circuitry
will power down the PWM controller causing the output voltage to decrease.
Following a time-out period the PWM will restart, causing the output voltage
to ramp to its appropriate value. If the fault condition persists, and the output
voltage again climbs to excessive levels, the overvoltage circuitry will initiate
another shutdown cycle. This on/off cycling is referred to as "hiccup" mode.
Output Overcurrent Detection
Overloading the power converter's output for an extended time will invariably
cause internal component temperatures to exceed their maximum ratings
and eventually lead to component failure. High-current-carrying components
such as inductors, FET's and diodes are at the highest risk. LEN D12 Series
DC/DC converters incorporate an output overcurrent detection and shutdown
function that serves to protect both the power converter and its load.
If the output current exceeds it maximum rating by typically 40% (35 Amps) or
if the output voltage drops to less than 98% of it original value, the LEN D12's
internal overcurrent-detection circuitry immediately turns off the converter,
which then goes into a "hiccup" mode. While hiccupping, the converter will
continuously attempt to restart itself, go into overcurrent, and then shut down.
Under these conditions, both the average output current and the average
input current will be kept extremely low. Once the output short is removed, the
converter will automatically restart itself.
Output Voltage Trimming
Allowable trim ranges for models
≥1.8V
OUT
are ±10%, and for models 1.5V
OUT
and lower +10%/–3% (no trim for 0.8V models). Trimming is accomplished
with either a trimpot or a single fixed resistor. The trimpot should be con-
nected between +Output and Common with its wiper connected to the Trim
pin as shown in Figure 4 below.
A trimpot can be used to determine the value of a single fixed resistor
½
½½½½½½½½½½½½
½½½½½½
½½½½
Note:
Install either a fixed
trim-up resistor
or a fixed trim-down
resistor depending upon
desired output voltage.
Figure 5. Trim Connections Using Fixed Resistors
Trim Equations
½½½½½½
½½
½½½½½½½
½
½½½½½
½½½½
½
½½½
½
½½½½½½½
½½½½½½
½½
½½½
½
½½
½½½
½½½½½
½½½
½½½½½½½½½½½½½½½
½½½½½½½½½
½½½½½½½½½½½½½½½½½
½½½½½½½½½
½½½½½½½½½½½½½½½½½
½½½½½½½½
½½½½½½½½½½½½½½½½½
½½½½½½½½
½½½½½½½½½½½½½½½
½½½½½½½½
½½½½½½½½½½½½½½
½
½½½½½½½½½½½½
½½½½½½
½½½½
½½½½½½
½½
½½½½½½½
½
½½½½½
½½½½
½
½½½½½½
½
½½½½½½½
½½½½½½
½½
½½½½½½
½
½½
½½½
½½½½½
½½½½½½
½
½½½½½½½½½½½½
½½½½½½
½½½½
½½½½½
½½
½½½½½½½
½
½½½½½
½½½½
½
½½½
½
½½½½½½½
½½½½½½
½½
½½
½
½½
½½½
½½½½½
½½½
½½½½½½½½½½½½½½½½½
½½½½½½½½
½½½½½½½½½½½½½½½
½½½½½½½½
Note: LEN-0.8/28-D12 is not trimmable.
Note: Resistor values are in kΩ. Accuracy of adjustment is subject to
tolerances of resistors and factory-adjusted, initial output accuracy.
V
O
= desired output voltage. V
ONOM
= nominal output voltage.
5
FPGA/CPLD
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