EEWORLDEEWORLDEEWORLD

Part Number

Search

530AB138M000DGR

Description
LVPECL Output Clock Oscillator, 138MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530AB138M000DGR Overview

LVPECL Output Clock Oscillator, 138MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AB138M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency138 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
My board has arrived, it is healthier to sunbathe
Finally received theGetting Started Guide card, the font is really bigThe data cable is praised :sexy:After unpacking, there is actually a small boardI don't know what it is used for nowThe interface ...
dql2016 DIY/Open Source Hardware
Good resources of the week (power supply category) February 5th week
:) It's time for the weekly push again~~ I hope every resource can be put to good use, and everyone can find what they need [url=https://download.eeworld.com.cn/detail/shenyuxiaoyu/559979]Switching Po...
okhxyyo Power technology
Introduction to FPGA design process and design considerations
Welcome to join the FPGA technology group: 63296979...
lpeng00007 FPGA/CPLD
Development of teaching equipment experiment box based on FPGA
[font=宋体][b]FPGA core board development and use manual, everyone discusses technology with each other[/b][/font] [[i] This post was last edited by yifan5156 on 2013-7-17 16:52[/i]]...
yifan5156 FPGA/CPLD
National IC Designer Certification Examination FAQs are hot! Haha
http://www.zfa.cn 2005-09-09 China Development Network reported1. What is IC design?Answer: IC design is simply hardware circuit design. Designers propose design ideas based on design requirements, an...
fighting FPGA/CPLD
UCP communication problem on wince
Can a PDA communicate with a PC via UDP via wireless? I wrote a UDP communication program using evc. When I send messages to myself on the PDA, it can be received, but when I send messages to the PC, ...
dule Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 773  591  1673  1109  349  16  12  34  23  8 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号