2.5 V to 5.5 V Octal Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308/AD5318/AD5328
FEATURES
AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL, B version: ±0.75 LSB INL
AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL, B version: ±3 LSB INL
AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL, B version: ±12 LSB INL
Low power operation: 0.7 mA @ 3 V
Guaranteed monotonic by design over all codes
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Double-buffered input logic
Buffered/unbuffered/V
DD
reference input options
Output range: 0 V to V
REF
or 0 V to 2 V
REF
Power-on reset to 0 V
Programmability
Individual channel power-down
Simultaneous update of outputs (LDAC)
Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-
compatible 3-wire serial interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308/
AD5318/AD5328 use a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface
standards.
The references for the eight DACs are derived from two
reference pins (one per DAC quad). These reference inputs can
be configured as buffered, unbuffered, or V
DD
inputs. The parts
incorporate a power-on reset circuit, which ensures that the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the current
consumption of the devices to 400 nA at 5 V (120 nA at 3 V).
The eight channels of the DAC may be powered down individually.
All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
AD5308/AD5318/AD5328
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
Digital-to-Analog Converter .................................................... 15
Resistor String ............................................................................. 15
Output Amplifier........................................................................ 15
Power-On Reset .......................................................................... 16
Power-Down Mode .................................................................... 16
Serial Interface ............................................................................ 16
Low Power Serial Interface ....................................................... 18
Load DAC Input (LDAC) Function......................................... 18
Double-Buffered Interface ........................................................ 18
Microprocessor Interface............................................................... 19
ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328
Interface ....................................................................................... 19
68HC11/68L11-to-AD5308/AD5318/AD5328 Interface ..... 19
80C51/80L51-to-AD5308/AD5318/AD5328 Interface......... 19
Microwire-to-AD5308/AD5318/AD5328 Interface.............. 20
Applications Information .............................................................. 21
Typical Application Circuit....................................................... 21
Driving V
DD
from the Reference Voltage ................................ 21
Bipolar Operation Using the AD5308/AD5318/AD5328..... 21
Opto-Isolated Interface for Process Control Applications ... 21
Decoding Multiple AD5308/AD5318/AD5328s.................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
3/07—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings Section......................... 7
9/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Change to Equation........................................................................ 21
11/03—Rev. A to Rev. B
Changes to Ordering Guide ............................................................ 4
Changes to Y axis on TPCs 12, 13, and 15 .................................... 9
8/03—Rev. 0 to Rev. A
Added A Version.................................................................Universal
Changes to Features.......................................................................... 1
Changes to Specifications ................................................................ 2
Edits to Absolute Maximum Ratings ............................................. 4
Edits to Ordering Guide .................................................................. 4
Updated Outline Dimensions ....................................................... 18
Rev. D | Page 2 of 24
AD5308/AD5318/AD5328
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
REF
ABCD
V
DD
GAIN-SELECT
LOGIC
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
SCLK
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
RESET
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DD
DAC H
BUFFER
V
OUT
D
DAC
REGISTER
STRING
DAC
REGISTER
DAC
REGISTER
STRING
BUFFER
DAC A
STRING
DAC B
STRING
DAC C
LDAC
BUFFER
V
OUT
A
BUFFER
V
OUT
B
BUFFER
V
OUT
C
SYNC
INTERFACE
LOGIC
BUFFER
V
OUT
E
DIN
BUFFER
V
OUT
F
BUFFER
V
OUT
G
BUFFER
GND
GAIN-SELECT
LOGIC
POWER-DOWN
LOGIC
V
OUT
H
V
DD
LDAC
V
REF
EFGH
GND
Figure 1.
Rev. D | Page 3 of 24
02812-001
POWER-ON
RESET
AD5308/AD5318/AD5328
SPECIFICATIONS
V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise specified.
Table 1.
Parameter
2
DC PERFORMANCE
3 , 4
AD5308
Resolution
Relative Accuracy
Differential Nonlinearity
AD5318
Resolution
Relative Accuracy
Differential Nonlinearity
AD5328
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
5
Min
A Version
1
Typ
Max
Min
B Version
1
Typ
Max
Unit
Conditions/Comments
8
±0.15
±0.02
±1
±0.25
8
±0.15
±0.02
±0.75
±0.25
Bits
LSB
LSB
Guaranteed monotonic by
design over all codes
10
±0.5
±0.05
±4
±0.50
10
±0.5
±0.05
±3
±0.50
Bits
LSB
LSB
Guaranteed monotonic by
design over all codes
12
±2
±0.2
±5
±0.30
10
±16
±1.0
±60
±1.25
60
12
±2
±0.2
±5
±0.30
10
±12
±1.0
±60
±1.25
60
Bits
LSB
LSB
mV
% of FSR
mV
Guaranteed monotonic by
design over all codes
V
DD
= 4.5 V, gain = 2, see
Figure 27
and
Figure 28
V
DD
= 4.5 V, gain = 2, see
Figure 27
and
Figure 28
Lower deadband exists only
if offset error is negative, see
Figure 27
Upper Deadband
5
10
60
10
60
mV
Upper deadband exists only
if V
REF
= V
DD
and offset plus
gain error is positive, see
Figure 28
Offset Error Drift
Gain Error Drift
6
DC Power Supply Rejection Ratio
6
DC Crosstalk
6
DAC REFERENCE INPUTS
6
V
REF
Input Range
V
REF
Input Impedance (R
DAC
)
37.0
18.0
Reference Feedthrough
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
7
Maximum Output Voltage
7
DC Output Impedance
6
−12
−5
−60
200
1.0
0.25
>10.0
45.0
22.0
−70.0
−75.0
0.001
V
DD
− 0.001
0.5
37.0
18.0
V
DD
V
DD
1.0
0.25
−12
−5
−60
200
V
DD
V
DD
>10.0
45.0
22.0
−70.0
−75.0
0.001
V
DD
− 0.001
0.5
ppm of
FSR/°C
ppm of
FSR/°C
dB
μV
V
V
MΩ
kΩ
kΩ
dB
dB
V
V
Ω
V
DD
= ±10%
R
L
= 2 kΩ to GND or V
DD
Buffered reference mode
Unbuffered reference mode
Buffered reference mode
and power-down mode
Unbuffered reference mode,
0 V to V
REF
output range
Unbuffered reference mode,
0 V to 2 V
REF
output range
Frequency = 10 kHz
Frequency = 10 kHz
This is a measure of the
minimum and maximum
Drive capability of the
output amplifier
Rev. D | Page 4 of 24
AD5308/AD5318/AD5328
Parameter
2
Short Circuit Current
Power-Up Time
Min
A Version
1
Typ
Max
25.0
16.0
2.5
5.0
LOGIC INPUTS
6
Input Current
V
IL
, Input Low Voltage
Min
B Version
1
Typ
25.0
16.0
2.5
5.0
Max
Unit
mA
mA
μs
μs
Conditions/Comments
V
DD
= 5 V
V
DD
= 3 V
Coming out of power-down
mode, V
DD
= 5 V
Coming out of power-down
mode, V
DD
= 3 V
±1
0.8
0.8
0.7
1.7
3.0
2.5
1.0
0.7
5.5
1.8
1.5
2.5
1.0
0.7
1.7
3.0
±1
0.8
0.8
0.7
V
IH
, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
8
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
μA
V
V
V
V
pF
V
DD
= 5 V ± 10%
V
DD
= 3 V ± 10%
V
DD
= 2.5 V
V
DD
= 2.5 V to 5.5 V, TTL and
CMOS compatible
5.5
1.8
1.5
V
mA
mA
V
IH
= V
DD
and V
IL
= GND
All DACs in unbuffered
mode, in buffered mode
Extra current is typically x μA
per DAC; x = (5 μA +
V
REF
/R
DAC
)/4
V
IH
= V
DD
and V
IL
= GND
I
DD
(Power-Down Mode)
9
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
1
2
0.4
0.12
1
1
0.4
0.12
1
1
μA
μA
Temperature range (A, B Version):
−
40°C to +105°C; typical at 25°C.
See the Terminology section.
3
DC specifications tested with the outputs unloaded unless stated otherwise.
4
Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).
5
This corresponds to x codes. x = deadband voltage/LSB size.
6
Guaranteed by design and characterization; not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V
REF
= V
DD
and offset plus
gain error must be positive.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All eight DACs powered down.
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. AC Characteristics
1
Parameter
3
Output Voltage Settling Time
AD5308
AD5318
AD5328
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
A, B Version
2
Min
Typ
Max
6
7
8
0.7
12
0.5
0.5
1
3
200
−70
8
9
10
Unit
μs
μs
μs
V/μs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
dB
Conditions/Comments
V
REF
= V
DD
= 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 To 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
V
REF
= 2 V ± 0.1 V p-p, unbuffered mode
V
REF
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
Guaranteed by design and characterization; not production tested.
Temperature range (A, B Version): –40°C to +105°C; typical at 25°C.
3
See the Terminology section.
Rev. D | Page 5 of 24
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