ICSLV810FIT datasheet, PDF - EEWORLD Datasheet

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ICSLV810FIT: DescriptionLow Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.209 INCH, SSOP-20; Categorylogic logic; File Size140KB，12 Pages; ManufacturerIDT (Integrated Device Technology)

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ICSLV810FIT Overview

Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.209 INCH, SSOP-20

ICSLV810FIT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SSOP
package instruction	SSOP, SSOP20,.3
Contacts	20
Reach Compliance Code	not_compliant
series	810
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	7.2 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
MaximumI(ol)	0.012 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP20,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225
power supply	2.5 V
Prop。Delay @ Nom-Sup	3.5 ns
propagation delay (tpd)	3.5 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	5.3 mm
minfmax	133 MHz

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ICSLV810

Buffer/Clock Driver

Description

The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout

buffer. This device is specifically designed for data

communications clock management. The large fanout

from a single input line reduces loading on the input

clock. The TTL level outputs reduce noise levels on the

part. Typical applications are clock and signal

distribution.

Features

•

Packaged in 20-pin QSOP/SSOP

•

Split 1:10 fanout Buffer

•

Maximum skew between outputs of different

•

packages 0.75 ns

Max propagation delay of 3.8 ns

Operating voltage of 1.5 V to 2.5 V on Bank A

Operating voltage of 1.5 V to 2.5 V on Banks B and C

Advanced, low power, CMOS process

Industrial temperature range -40° C to +85° C

3.3 V tolerant input when VDDA=2.5 V

Available in Pb (lead) free packaging

Block Diagram

VDDA

CLK 1

CLK 2

CLK 3

CLK 4

CLKIN

CLK 5

CLK 6

CLK 7

CLK 8

CLK 9

CLK 10

VDDB

VDDC

MDS LV810 F

Integrated Circuit Systems, Inc.

●

525 Race Street, San Jose, CA 95126

●

Revision 101305

tel (408) 297-1201

●

www.icst.com

ICSLV810FIT Related Products

	ICSLV810FIT	ICSLV810RILFT	ICSLV810RILF	ICSLV810FILFT	ICSLV810FILF
Description	Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.209 INCH, SSOP-20	Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, QSOP-20	Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, ROHS COMPLIANT, QSOP-20	Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.209 INCH, ROHS COMPLIANT, SSOP-20	Low Skew Clock Driver, 810 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.209 INCH, LEAD FREE, SSOP-20
Is it lead-free?	Contains lead	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	incompatible	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	SSOP	QSOP	QSOP	SSOP	SSOP
package instruction	SSOP, SSOP20,.3	SSOP, SSOP20,.25	SSOP, SSOP20,.25	SSOP, SSOP20,.3	SSOP, SSOP20,.3
Contacts	20	20	20	20	20
Reach Compliance Code	not_compliant	compliant	compliant	compliant	compliant
series	810	810	810	810	810
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e0	e3	e3	e3	e3
length	7.2 mm	8.65 mm	8.65 mm	7.2 mm	7.2 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
MaximumI(ol)	0.012 A	0.012 A	0.012 A	0.012 A	0.012 A
Humidity sensitivity level	1	1	1	1	1
Number of functions	1	1	1	1	1
Number of terminals	20	20	20	20	20
Actual output times	10	10	10	10	10
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP	SSOP	SSOP	SSOP
Encapsulate equivalent code	SSOP20,.3	SSOP20,.25	SSOP20,.25	SSOP20,.3	SSOP20,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	225	260	260	260	260
power supply	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Prop。Delay @ Nom-Sup	3.5 ns	3.5 ns	3.5 ns	3.5 ns	3.5 ns
propagation delay (tpd)	3.5 ns	3.5 ns	3.5 ns	3.5 ns	3.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns	0.2 ns	0.2 ns	0.2 ns	0.2 ns
Maximum seat height	2 mm	1.75 mm	1.75 mm	2 mm	2 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.635 mm	0.635 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30
width	5.3 mm	3.9 mm	3.9 mm	5.3 mm	5.3 mm
minfmax	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz
ECCN code	-	EAR99	EAR99	EAR99	-

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