LCK4801 datasheet, PDF - EEWORLD Datasheet

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LCK4801: DescriptionClock Generator, 1000MHz, CMOS, PQFP32, TQFP-32; CategoryThe embedded processor and controller Microcontrollers and processors; File Size171KB，10 Pages; ManufacturerBroadcom

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LCK4801 Overview

Clock Generator, 1000MHz, CMOS, PQFP32, TQFP-32

LCK4801 Parametric

Parameter Name	Attribute value
Maker	Broadcom
package instruction	LQFP,
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G32
JESD-609 code	e0
length	7 mm
Number of terminals	32
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	1000 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
Master clock/crystal nominal frequency	125 MHz
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

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Preliminary Data Sheet

December 2001

LCK4801

Low-Voltage HSTL Differential Clock

General

The LCK4801 is a low-voltage, 3.3 V HSTL

differential clock synthesizer. The LCK4801 supports

two differential HSTL output pairs with frequencies

from 336 MHz to 1 GHz. The clock is designed to

support single and multiple processor systems that

require HSTL differential inputs. The LCK4801

contains a fully integrated PLL (phase-locked loop)

which multiplies the HSTL_CLK or PECL_CLK input

frequency to match individual processor clock

frequencies. The PLL can be bypassed so that the

PCLK outputs are fed from the HSTL_CLK or

PECL_CLK input for test purposes. All outputs are

powered from a 2 V external supply to reduce on-

chip power consumption. All outputs are HSTL. The

PLL can operate in the internal feedback mode, or in

the external feedback mode for board level

debugging applications.

Features

Two fully selectable clock inputs.

Fully integrated PLL.

336 MHz to 1 GHz output frequencies.

HSTL outputs.

HSTL and LVPECL reference clocks.

32-pin TQFP package.

Pin compatible with

Motorola

MPC998.

Agere Systems Inc. chip has expanded frequency

range and improved performance:

— MPC998 range is 520 MHz—840MHz.

— LCK4801 range is 336 MHz—1 GHz.

Description

PCLK0_EN (PULL-UP)

PCLK1_EN (PULL-UP)

TESTM (PULL-UP)

PLLREF_EN (PULL-UP)

REF_SEL (PULL-UP)

HSTL_CLK (PULL-UP)

PECL_CLK (PULL-UP)

(PULL-UP)

EXTFB_IN (HSTL)

(PULL-DOWN)

EXTFB_EN (PULL-UP)

EXTFB_OUT (HSTL)

SEL[4:0] (PULL-UP)

RESET (PULL-UP)

PLL_BYPASS (PULL-UP)

2274.a (F)

PLL

PCLK0

PCLK0 (HSTL)

PCLK1

PCLK1 (HSTL)

EXTFB_OUT

DECODE

Figure 1. LCK4801 Logic Diagram

LCK4801 Related Products

	LCK4801
Description	Clock Generator, 1000MHz, CMOS, PQFP32, TQFP-32
Maker	Broadcom
package instruction	LQFP,
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G32
JESD-609 code	e0
length	7 mm
Number of terminals	32
Maximum operating temperature	70 °C
Maximum output clock frequency	1000 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
Master clock/crystal nominal frequency	125 MHz
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

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