FLDMT-TTL-30 datasheet, PDF - EEWORLD Datasheet

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FLDMT-TTL-30: DescriptionActive Delay Line, 1-Func, 5-Tap, True Output, TTL, PDIP8, 0.150 INCH HEIGHT, PLASTIC,MODULE, DIP-14/8; Categorylogic logic; File Size36KB，1 Pages; ManufacturerEngineered Components Co.

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FLDMT-TTL-30 Overview

Active Delay Line, 1-Func, 5-Tap, True Output, TTL, PDIP8, 0.150 INCH HEIGHT, PLASTIC,MODULE, DIP-14/8

FLDMT-TTL-30 Parametric

Parameter Name	Attribute value
Maker	Engineered Components Co.
Parts packaging code	DIP
package instruction	DIP,
Contacts	14/8
Reach Compliance Code	unknown
Other features	TYP. ICC = 40MA; INTERNAL TERMINATION; MAX RISE TIME CAPTURED
series	F
JESD-30 code	R-PDIP-P8
length	20.32 mm
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
programmable delay line	NO
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	DUAL
Total delay nominal (td)	30 ns
width	7.62 mm

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FAST TTL Logic Delay Module (Thin Profile Package)

The FAST TTL Logic Delay Modules (Thin Profile Package) manufactured by Engineered Components Company

are designed to provide output waveforms that reproduce the input waveform after a set amount of delay

time has elapsed. The five output waveforms are delay line taps provided at 20% increments of the total

delay (20, 40, 60, 80, and 100%). These delay modules are non-inverting. The delay times are calibrated

to the listed tolerances on the rising edge delays. The products with a total delay of less than 25ns have

additional delay present at tap 1 due to internal propagation delays (see the Product Selection Table).

The MTBF on these modules, when calculated per MIL-HDBK-217, for a 50 deg.C ground fixed environment and

with 50VDC applied, is in excess of 2 million hours. The temperature coefficient of delay is less than

500 ppm/deg.C over the operating temperature range of 0 to +70 deg. C.

The module is provided in a 14-pin DIP package, fully encapsulated in epoxy resin and is housed in a Diallyl

Phthalate case, blue in color. The case marking is applied by silkscreen using white epoxy paint. The 8

copper leads are tin-lead plated and meet the solderability requirements of MIL-STD-202, Method 208.

BLOCK DIAGRAM

MECHANICAL DIAGRAM

Output

Buffer

Input

Buffer

.150 TYP.

Delay Line

Output Output Output Output

Buffer Buffer Buffer Buffer

.060 TYP.

.300

.020 DIA. TYP.

.100 TYP.

.300 TYP.

.150

Product Selection Table

Part

Output Delay and Tolerances (in ns)

Number

Tap 1(20%) Tap 2 (40%) Tap 3 (60%) Tap 4 (80%) Tap 5 (100%)

FLDMT-TTL-10

6.0+/-1.0

7.0+/-1.0

8.0+/-1.0

9.0+/-1.0

10.0+/-1.0

FLDMT-TTL-12

6.0+/-1.0

7.5+/-1.0

9.0+/-1.0

10.5+/-1.0

12.0+/-1.0

FLDMT-TTL-14

6.0+/-1.0

8.0+/-1.0 10.0+/-1.0 12.0+/-1.0

14.0+/-1.0

FLDMT-TTL-16

6.0+/-1.0

8.5+/-1.0 11.0+/-1.0 13.5+/-1.0

16.0+/-1.0

FLDMT-TTL-18

6.0+/-1.0

9.0+/-1.0 12.0+/-1.0 15.0+/-1.0

18.0+/-1.0

FLDMT-TTL-22

6.0+/-1.0 10.0+/-1.0 14.0+/-1.0 18.0+/-1.0

22.0+/-1.0

FLDMT-TTL-25

5.0+/-1.0 10.0+/-1.0 15.0+/-1.0 20.0+/-1.0

25.0+/-1.0

FLDMT-TTL-30

6.0+/-1.0 12.0+/-1.0 18.0+/-1.0 24.0+/-1.0

30.0+/-1.5

FLDMT-TTL-35

7.0+/-1.0 14.0+/-1.0 21.0+/-1.0 28.0+/-1.5

35.0+/-1.5

FLDMT-TTL-40

8.0+/-1.0 16.0+/-1.0 24.0+/-1.0 32.0+/-1.5

40.0+/-2.0

FLDMT-TTL-45

9.0+/-1.0 18.0+/-1.0 27.0+/-1.5 36.0+/-1.5

45.0+/-2.0

FLDMT-TTL-50

10.0+/-1.0 20.0+/-1.0 30.0+/-1.5 40.0+/-2.0

50.0+/-2.0

FLDMT-TTL-55

11.0+/-1.0 22.0+/-1.0 33.0+/-1.5 44.0+/-2.0

55.0+/-2.0

FLDMT-TTL-60

12.0+/-1.0 24.0+/-1.0 36.0+/-1.5 48.0+/-2.0

60.0+/-2.0

FLDMT-TTL-65

13.0+/-1.0 26.0+/-1.5 39.0+/-1.5 52.0+/-2.0

65.0+/-2.5

FLDMT-TTL-70

14.0+/-1.0 28.0+/-1.5 42.0+/-2.0 56.0+/-2.0

70.0+/-2.5

FLDMT-TTL-75

15.0+/-1.0 30.0+/-1.5 45.0+/-2.0 60.0+/-2.0

75.0+/-2.5

FLDMT-TTL-80

16.0+/-1.0 32.0+/-1.5 48.0+/-2.0 64.0+/-2.5

80.0+/-3.0

FLDMT-TTL-85

17.0+/-1.0 34.0+/-1.5 51.0+/-2.0 68.0+/-2.5

85.0+/-3.0

FLDMT-TTL-90

18.0+/-1.0 36.0+/-1.5 54.0+/-2.0 72.0+/-2.5

90.0+/-3.0

FLDMT-TTL-95

19.0+/-1.0 38.0+/-1.5 57.0+/-2.0 76.0+/-2.5

95.0+/-3.0

FLDMT-TTL-100 20.0+/-1.0 40.0+/-1.5 60.0+/-2.0 80.0+/-3.0 100.0+/-3.0

FLDMT-TTL-125 25.0+/-1.0 50.0+/-2.0 75.0+/-2.5 100.0+/-3.0 125.0+/-4.0

FLDMT-TTL-150 30.0+/-1.5 60.0+/-2.0 90.0+/-3.0 120.0+/-4.0 150.0+/-5.0

FLDMT-TTL-175 35.0+/-1.5 70.0+/-2.5 105.0+/-4.0 140.0+/-4.5 175.0+/-5.0

FLDMT-TTL-200 40.0+/-1.5 80.0+/-3.0 120.0+/-4.0 160.0+/-5.0 200.0+/-6.0

FLDMT-TTL-225 45.0+/-2.0 90.0+/-3.0 135.0+/-4.0 180.0+/-6.0 225.0+/-7.0

FLDMT-TTL-250 50.0+/-2.0 100.0+/-3.0 150.0+/-5.0 200.0+/-6.0 250.0+/-8.0

Special modules can often be manufactured to provide for customer specific applications.

.400

FLDMT-TTL-25

4 C

Operating Specifications:

All measurements made at 25 deg. C

All measurements made with Vcc = +5VDC

All measurements made with (1) FAST TTL output load

Operating Temperature: 0 to +70 deg. C

Storage Temperature: -55 to +125 deg. C

Vcc Supply Voltage: 4.75 to 5.25VDC

Vcc Supply Current:

Constant “0” in = 40mA typical

Constant “1” in = 7mA typical

Logic “High” Input:

Voltage: 2.0VDC min. ; Vcc max.

Current: 2.7VDC = 20uA max. ; 5.5VDC = 1mA max.

Logic “Low” Input:

Voltage: 0.8 VDC max.

Current: -0.6mA max.

Logic “High” Voltage Out: 2.7VDC min.

Logic “Low” Voltage Out: 0.5VDC max.

Phone: 805-369-0034

Fax:

805-369-0033

Web: www.ec2.com

engineered components company

A Division of Cornucopia Tool & Plastics, Inc. PO Box 1915, 448 Sherwood Rd., Paso Robles CA 93447

YYWW

.020

DATE CODE

3 OUT

+/-.020

.130

Top view

.800

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