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DS2156
T1/E1/J1 Single-Chip Transceiver
TDM/UTOPIA II Interface
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1
single-chip transceiver (SCT) for short-haul and
long-haul applications. The backplane is user-
configurable for a TDM or UTOPIA II bus interface.
The DS2156 is composed of a line interface unit
(LIU), framer, HDLC controllers, and a
UTOPIA/TDM backplane interface, and is controlled
by an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS2156 is pin and
software compatible with the DS2155.
The LIU is composed of transmit and receive
interfaces and a jitter attenuator. The transmit
interface is responsible for generating the necessary
waveshapes for driving the network and providing
the correct source impedance depending on the type
of media used. T1 waveform generation includes
DSX-1 line buildouts as well as CSU line buildouts
of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω
coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and
data from the network.
FEATURES
Complete T1/DS1/ISDN-PRI/J1 Transceiver
Functionality
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
User-Selectable TDM or UTOPIA II Bus
Interface
Long-Haul and Short-Haul Line Interface for
Clock/Data Recovery and Waveshaping
CMI Coder/Decoder for Optical I/F
Crystal-Less Jitter Attenuator
Fully Independent Transmit and Receive
Functionality
Dual HDLC Controllers
Programmable BERT Generator and Detector
Internal Software-Selectable Receive and
Transmit-Side Termination Resistors for
75Ω/100Ω/120Ω T1 and E1 Interfaces
Dual Two-Frame Elastic-Store Slip Buffers that
Connect to Asynchronous Backplanes Up to
16.384MHz
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
Features continued in Section
1.
APPLICATIONS
Inverse Mux ATM (IMA)
T1/E1/J1 Line Cards
Switches and Routers
Add-Drop Multiplexers
ORDERING INFORMATION
PART
DS2156L
DS2156L+
DS2156LN
DS2156LN+
DS2156G
DS2156G+
DS2156GN
DS2156GN+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
100 LQFP
100 LQFP
100 LQFP
100 LQFP
100 CSBGA
100 CSBGA
100 CSBGA
100 CSBGA
UTOPIA
T1/E1/J1
NETWORK
DS2156
T1/E1/J1
TDM/UTOPIA
BACKPLANE
TDM
+Denotes
lead-free/RoHS-compliant package.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 011606
DS2156
TABLE OF CONTENTS
1.
2.
2.1
MAIN FEATURES............................................................................................................ 9
DETAILED DESCRIPTION............................................................................................ 12
B
LOCK
D
IAGRAM
........................................................................................................................ 14
3.
3.1
PIN FUNCTION DESCRIPTION .................................................................................... 20
TDM B
ACKPLANE
...................................................................................................................... 20
Transmit Side .......................................................................................................................................20
Receive Side ........................................................................................................................................23
3.1.1
3.1.2
3.2
3.2.1
3.2.2
UTOPIA B
US
............................................................................................................................ 26
Receive Side ........................................................................................................................................26
Transmit Side .......................................................................................................................................27
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
P
ARALLEL
C
ONTROL
P
ORT
P
INS
................................................................................................ 28
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
...................................................................................... 29
U
SER
O
UTPUT
P
ORT
P
INS
......................................................................................................... 30
JTAG T
EST
A
CCESS
P
ORT
P
INS
................................................................................................ 31
L
INE
I
NTERFACE
P
INS
................................................................................................................ 32
S
UPPLY
P
INS
............................................................................................................................. 33
L
AND
G P
ACKAGE
P
INOUT
........................................................................................................ 34
10
MM
CSBGA P
IN
C
ONFIGURATION
.......................................................................................... 38
4.
4.1
4.2
PARALLEL PORT ......................................................................................................... 39
R
EGISTER
M
AP
.......................................................................................................................... 39
UTOPIA B
US
R
EGISTERS
.......................................................................................................... 45
5.
6.
6.1
6.2
6.3
6.4
6.5
SPECIAL PER-CHANNEL REGISTER OPERATION ................................................... 46
PROGRAMMING MODEL ............................................................................................. 48
P
OWER
-U
P
S
EQUENCE
.............................................................................................................. 49
Master Mode Register..........................................................................................................................49
6.1.1
I
NTERRUPT
H
ANDLING
............................................................................................................... 50
S
TATUS
R
EGISTERS
................................................................................................................... 50
I
NFORMATION
R
EGISTERS
.......................................................................................................... 51
I
NTERRUPT
I
NFORMATION
R
EGISTERS
........................................................................................ 51
7.
8.
8.1
8.2
8.3
8.4
CLOCK MAP.................................................................................................................. 52
T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS ........................... 53
T1 C
ONTROL
R
EGISTERS
........................................................................................................... 53
T1 T
RANSMIT
T
RANSPARENCY
................................................................................................... 58
AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
..................................................................... 58
T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
......................................................... 59
9.
9.1
9.2
9.3
E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS........................... 62
E1 C
ONTROL
R
EGISTERS
.......................................................................................................... 62
A
UTOMATIC
A
LARM
G
ENERATION
............................................................................................... 66
E1 I
NFORMATION
R
EGISTERS
.................................................................................................... 67
10.
10.1
COMMON CONTROL AND STATUS REGISTERS ...................................................... 69
T1/E1 S
TATUS
R
EGISTERS
........................................................................................................ 70
11.
12.
12.1
I/O PIN CONFIGURATION OPTIONS ........................................................................... 76
LOOPBACK CONFIGURATION.................................................................................... 78
P
ER
-C
HANNEL
L
OOPBACK
......................................................................................................... 80
13.
13.1
ERROR COUNT REGISTERS ....................................................................................... 82
L
INE
-C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(LCVCR) ................................................................... 83
T1 Operation ........................................................................................................................................83
E1 Operation ........................................................................................................................................83
13.1.1
13.1.2
13.2
P
ATH
C
ODE
V
IOLATION
C
OUNT
R
EGISTER
(PCVCR) .................................................................. 85
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DS2156
13.2.1
13.2.2
T1 Operation ........................................................................................................................................85
E1 Operation ........................................................................................................................................85
13.3
13.3.1
13.3.2
F
RAMES
O
UT
-
OF
-S
YNC
C
OUNT
R
EGISTER
(FOSCR).................................................................. 86
T1 Operation ........................................................................................................................................86
E1 Operation ........................................................................................................................................86
13.4
E-B
IT
C
OUNTER
(EBCR) ........................................................................................................... 87
14.
15.
15.1
DS0 MONITORING FUNCTION..................................................................................... 88
SIGNALING OPERATION ............................................................................................. 90
R
ECEIVE
S
IGNALING
.................................................................................................................. 90
Processor-Based Signaling..................................................................................................................90
Hardware-Based Receive Signaling ....................................................................................................91
15.1.1
15.1.2
15.2
15.2.1
15.2.2
15.2.3
15.2.4
T
RANSMIT
S
IGNALING
................................................................................................................ 96
Processor-Based Mode .......................................................................................................................96
Software Signaling Insertion-Enable Registers, E1 CAS Mode ........................................................100
Software Signaling Insertion-Enable Registers, T1 Mode .................................................................102
Hardware-Based Mode ......................................................................................................................102
16.
16.1
PER-CHANNEL IDLE CODE GENERATION .............................................................. 103
I
DLE
-C
ODE
P
ROGRAMMING
E
XAMPLES
..................................................................................... 104
17.
18.
18.1
CHANNEL BLOCKING REGISTERS .......................................................................... 108
ELASTIC STORES OPERATION ................................................................................ 111
R
ECEIVE
S
IDE
......................................................................................................................... 114
T1 Mode .............................................................................................................................................114
E1 Mode.............................................................................................................................................114
18.1.1
18.1.2
18.2
18.2.1
18.2.2
T
RANSMIT
S
IDE
....................................................................................................................... 114
T1 Mode .............................................................................................................................................115
E1 Mode.............................................................................................................................................115
18.3
18.4
E
LASTIC
S
TORES
I
NITIALIZATION
.............................................................................................. 115
M
INIMUM
D
ELAY
M
ODE
............................................................................................................ 115
19.
20.
20.1
20.2
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).................................. 116
T1 BIT-ORIENTED CODE (BOC) CONTROLLER ...................................................... 117
T
RANSMIT
BOC ....................................................................................................................... 117
R
ECEIVE
BOC ......................................................................................................................... 117
Transmit a BOC................................................................................................................................................117
Receive a BOC.................................................................................................................................................117
21.
21.1
21.2
21.3
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY).......... 120
M
ETHOD
1: H
ARDWARE
S
CHEME
............................................................................................. 120
M
ETHOD
2: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
D
OUBLE
-F
RAME
...................................... 120
M
ETHOD
3: I
NTERNAL
R
EGISTER
S
CHEME
B
ASED ON
CRC4 M
ULTIFRAME
................................ 123
22.
22.1
22.2
HDLC CONTROLLERS ............................................................................................... 133
B
ASIC
O
PERATION
D
ETAILS
..................................................................................................... 133
HDLC C
ONFIGURATION
........................................................................................................... 133
FIFO Control ......................................................................................................................................137
22.2.1
22.3
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
HDLC M
APPING
...................................................................................................................... 138
Receive ..............................................................................................................................................138
Transmit .............................................................................................................................................140
FIFO Information ................................................................................................................................145
Receive Packet-Bytes Available ........................................................................................................145
HDLC FIFOs ......................................................................................................................................146
22.4
22.5
22.5.1
22.5.2
22.5.3
R
ECEIVE
HDLC C
ODE
E
XAMPLE
.............................................................................................. 147
L
EGACY
FDL S
UPPORT
(T1 M
ODE
).......................................................................................... 147
Overview ............................................................................................................................................147
Receive Section .................................................................................................................................147
Transmit Section ................................................................................................................................149
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DS2156
22.6
D4/SLC-96 O
PERATION
.......................................................................................................... 149
23.
23.1
23.2
LINE INTERFACE UNIT (LIU) ..................................................................................... 150
LIU O
PERATION
...................................................................................................................... 150
R
ECEIVER
............................................................................................................................... 150
Receive Level Indicator and Threshold Interrupt ...............................................................................151
Receive G.703 Synchronization Signal (E1 Mode)............................................................................151
Monitor Mode .....................................................................................................................................151
23.2.1
23.2.2
23.2.3
23.3
23.3.1
23.3.2
23.3.3
23.3.4
T
RANSMITTER
.......................................................................................................................... 152
Transmit Short-Circuit Detector/Limiter..............................................................................................152
Transmit Open-Circuit Detector .........................................................................................................152
Transmit BPV Error Insertion .............................................................................................................152
Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................152
23.4
23.5
23.6
23.7
23.8
23.9
MCLK P
RESCALER
.................................................................................................................. 153
J
ITTER
A
TTENUATOR
............................................................................................................... 153
CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
.................................................................................... 153
LIU C
ONTROL
R
EGISTERS
....................................................................................................... 154
R
ECOMMENDED
C
IRCUITS
........................................................................................................ 161
C
OMPONENT
S
PECIFICATIONS
.................................................................................................. 163
24.
24.1
UTOPIA BACKPLANE INTERFACE........................................................................... 168
D
ESCRIPTION
.......................................................................................................................... 168
List of Applicable Standards ..............................................................................................................168
Acronyms and Definitions ..................................................................................................................168
24.1.1
24.1.2
24.2
24.3
24.4
24.5
24.5.1
24.5.2
24.5.3
UTOPIA C
LOCK
M
ODES
.......................................................................................................... 169
F
ULL
T1/E1 M
ODE AND
C
LEAR
-C
HANNEL
E1 M
ODE
................................................................. 169
F
RACTIONAL
T1/E1
MODE
........................................................................................................ 170
T
RANSMIT
O
PERATION
............................................................................................................. 171
UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV.......................................................171
UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV) ...................................................174
Transmit Processing ..........................................................................................................................176
24.6
24.6.1
24.6.2
24.6.3
R
ECEIVE
O
PERATION
............................................................................................................... 177
Receive Processing ...........................................................................................................................177
UTOPIA Side Receive: Muxed Mode with One Receive CLAV.........................................................179
UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV) .....................................................180
24.7
24.8
24.9
R
EGISTER
D
EFINITIONS
........................................................................................................... 182
R
ECEIVE
FIFO O
VERRUN
........................................................................................................ 193
UTOPIA D
IAGNOSTIC
L
OOPBACK
............................................................................................ 193
25.
26.
26.1
26.2
26.3
26.4
26.5
26.6
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ........ 194
BERT FUNCTION ........................................................................................................ 201
S
TATUS
................................................................................................................................... 201
M
APPING
................................................................................................................................. 201
BERT R
EGISTER
D
ESCRIPTIONS
............................................................................................. 203
BERT R
EPETITIVE
P
ATTERN
S
ET
............................................................................................. 207
BERT B
IT
C
OUNTER
............................................................................................................... 208
BERT E
RROR
C
OUNTER
......................................................................................................... 209
27.
27.1
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)................................ 211
N
UMBER
-
OF
-E
RRORS
R
EGISTERS
............................................................................................ 213
Number-of-Errors Left Register..........................................................................................................214
27.1.1
28.
28.1
28.2
INTERLEAVED PCM BUS OPERATION (IBO)........................................................... 215
C
HANNEL
I
NTERLEAVE
............................................................................................................. 215
F
RAME
I
NTERLEAVE
................................................................................................................. 215
29.
30.
31.
EXTENDED SYSTEM INFORMATION BUS (ESIB).................................................... 218
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER....................................... 222
FRACTIONAL T1/E1 SUPPORT ................................................................................. 222
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