M630x Series
QiK Chip™
5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/CMOS, TCXO/TCVCXO
Features:
TCXO/TCVCXO Featuring
QiK
Chip
TM
Technology
Superior Jitter Performance
(comparable to SAW based)
Frequencies from 50 MHz to 1.4 GHz
Designed for a short 2 week cycle
time
Applications:
Telecommunications such as SONET
/ SDH / DWDM / FEC / SERDES /
OC-3 thru OC-192
Wireless base stations / WLAN /
Gigabit Ethernet
Avionic flight controls and military
communications
, CMOS)
, CMOS)
Temperature vs. Stability
T
S
A = Available
N = Contact Factory
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
1-800-762-8800.
Revision: 3-24-09
M630x Series
5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/CMOS, TCXO/TCVCXO
Parameter
Frequency Range
Operating Temperature
Storage Temperature
Frequency Stability
Frequency Tolerance at +25°
C
Frequency Vs. Aging
Frequency Vs. Supply Voltage
Frequency Vs. Reflow
Frequency Vs. Load
Operating Voltage
Symbol
F
T
A
T
STG
Min.
Typ.
Max.
50
1400
50
135
See Ordering Information
-55
+125
See Ordering Information
-1.0
+1.0
-3.0
+ 3.0
-1.0
+ 1.0
± 0.4
±
0.75
± 0.2
3.135
3.3
3.465
2.375
2.5
2.625
1.71
1.8
1.89
125
100
110
90
0.35
6
V
CC
-1.02
90% V
dd
V
CC
-1.63
10% V
dd
1.2
45
55
45
55
45
55
0.7
0.95
1.2
±5
20
15
20
50
to (V
CC
-2)
VDC 100
Differential
15
80%
0.5
0.5
Phase Noise (Typical)
@ 622.080 MHz (LVPECL)
@ 100.000 MHz (HCMOS)
@ 50.000 MHZ (HCMOS)
10 Hz
-60
-73
-80
80%
100 Hz
-90
-97
-102
1 kHz
-120
-123
-130
10 kHz
-127
-131
-137
Units
MHz
MHz
°
C
°
C
ppm
ppm
ppm
ppm
ppm
ppm
ppm
V
V
V
mA
mA
mA
mA
ns
ns
V
V
V
V
V
%
%
%
Vp-p
ppm
ps
ps
ps
Conditions/Notes
LVPECL, LVDS, CML (Note 4)
CMOS
See Note 1
1 year
Per year thereafter.
5% voltage variation
2 reflows max.
5% supply voltage variation
M6300
M6301
M6302
LVPECL
LVDS
CML
CMOS
PECL, LVPECL, LVDS
CMOS
LVPECL
CMOS
LVPECL
CMOS
LVDS
@ 50% Vdd (CMOS)
@ 50% of waveform (LVPECL)
@ 1.25 V (LVDS)
CML
VCTCXO only. See Note 2.
LVPECL
CML
LVDS
See Note 3
LVPECL
LVDS, CML
CMOS
Outputs enabled (Option B or G)
Outputs disabled
Outputs enabled (Option S or M)
Outputs disabled
Offset from carrier
dBc/Hz
dBc/Hz
dBc/Hz
st
V
cc
/V
s
/V
dd
Operating Current
I
CC
Electrical Specifications
Rise/Fall Time
Logic “1” Level
Logic “0” Level
Common Mode Output Voltage
Symmetry (Duty Cycle)
Tr/Tf
V
OH
V
OL
Vcm
Output Voltage Level
Tuning Range
Output Skew
Output Load
pF
V
V
100 kHz
-133
-136
-141
Enable/Disable Function
Shock
Per MIL-STD-202, Method 213, Condition C
Vibration
Per MIL-STD-202, Methods 201 & 204
Solderability
Per EIAJ-STD-002
-8
Hermeticity
1 X 10 atm cc/sec of helium (Crystal only)
Thermal Shock
Per MIL-STD-883, Method 1011, Condition A
Thermal Cycle
Per MIL-STD-883, Method 1010, Condition B
Note 1: Contact factory for less than ± 1ppm frequency stability.
Note 2: Contact factory for other Tuning Range options.
Note 3: See Load Circuit Diagram in this data sheet.
Note 4: Contact factory for frequencies over 945 MHz.
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Environmental
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
1-800-762-8800.
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
