ST72321AR6TC/XXXE datasheet, PDF - EEWORLD Datasheet

EEWORLDEEWORLD

Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> ST72321AR6TC/XXXE

PDF

ST72321AR6TC/XXXE: Description8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，243 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

Download Datasheet Parametric View All

ST72321AR6TC/XXXE Overview

8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

ST72321AR6TC/XXXE Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	64
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G64
length	10 mm
Number of I/O lines	48
Number of terminals	64
On-chip program ROM width	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
RAM (bytes)	1024
rom(word)	32768
ROM programmability	MROM
Maximum seat height	1.6 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	3.8 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

Preview

Download Datasheet

ST72321xx-Auto

8-bit MCU for automotive with 32/60 Kbyte Flash/ROM,

ADC, 5 timers, SPI, SCI, I2C interface

Features

Memories

■

32 to 60 Kbyte dual voltage High Density Flash

(HDFlash) or ROM ROM with readout

protection capability. In-application

programming and in-circuit programming for

HDFlash devices

■

1 to 2 Kbyte RAM

■

HDFlash endurance: 100 cycles, data retention

20 years

LQFP64

10 x 10

LQFP64

14 x 14

LQFP44

10 x 10

5 timers

■

Clock, reset and supply management

■

Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

■

Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and bypass

for external clock

■

PLL for 2x frequency multiplication

■

4 power saving modes: Halt, Active Halt, Wait

and Slow

Main clock controller with Real-time base,

Beep and Clock-out capabilities

■

Configurable watchdog timer

■

Two 16-bit timers with 2 input captures, 2

output compares, external clock input on 1

timer, PWM and pulse generator modes

■

8-bit PWM auto-reload timer with 2 input

captures, 4 PWM outputs, output compare and

time base interrupt, external clock with event

detector

3 communications interfaces

■

Interrupt management

■

SPI synchronous serial interface

■

SCI asynchronous serial interface

■

I

2

C multimaster interface

Nested interrupt controller

■

14 interrupt vectors plus TRAP and RESET

■

Top Level Interrupt (TLI) pin on 64-pin devices

■

15 external interrupt lines (on 4 vectors)

Instruction set

■

1 analog peripheral

■

8-bit data manipulation

■

63 basic instructions

■

17 main addressing modes

■

8x8 unsigned multiply instruction

10-bit ADC with up to 16 input ports

Development tools

■

Up to 48 I/O ports

■

48//32 multifunctional bidirectional I/O lines

■

34//22 alternate function lines

■

16//12 high sink outputs

Full hardware/software development package,

ICT capability

Device summary

Part number

Table 1.

Reference

ST72321AR6-Auto,

ST72321R6-Auto,

ST72321AR7-Auto,

ST72321xx-Auto

ST72321J7-Auto, ST72321R7-Auto

ST72321AR9-Auto,

ST72321J9-Auto, ST72321R9-Auto

August 2010

Doc ID 13829 Rev 1

1/243

www.st.com

1

Contents

ST72321xx-Auto

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1

2.2

Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3

4

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3.1

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1

5.2

5.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1

6.2

6.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2/243

Doc ID 13829 Rev 1

ST72321xx-Auto

Contents

6.4

6.5

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 41

Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 47

7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.1

7.2

7.3

7.4

7.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5.1

7.5.2

CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 54

7.6

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.6.1

7.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 59

8

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.1

8.2

8.3

8.4

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.4.1

8.4.2

Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Doc ID 13829 Rev 1

3/243

Contents

ST72321xx-Auto

9.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.3

9.4

9.5

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 80

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.9.1

Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

11

Main clock controller with real-time clock and beeper (MCC/RTC) . . 82

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.8.1

11.8.2

MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 84

MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 85

12

PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.1

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Doc ID 13829 Rev 1

4/243

ST72321xx-Auto

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.2.7

12.2.8

12.2.9

Contents

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 90

External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 90

Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.3

ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . . 96

Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

13

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13.1

13.2

13.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.3.1

13.3.2

13.3.3

13.3.4

13.3.5

13.3.6

13.3.7

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.4

13.5

13.6

13.7

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.7.1

13.7.2

13.7.3

Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Doc ID 13829 Rev 1

5/243

Recommended Resources

Circuit design of electronic imitation mouse repeller

SH-803 Holiday Lights ASIC

SL517 (electronic toys) audio, radio frequency or infrared decoding circuit

Household carrier telephone circuit-b

Color TV adds AV output socket

555 100w inverter and charging circuit

Cypress PSoC4 Cortex-M0 Experience Contest! Oscium oscilloscope + 5000 yuan cash waiting for you! (Ended): [font=微软雅黑][size=5][url=https://bbs.eeworld.com.cn/thread-426802-1-1.html]【Award Ceremony】Cypress PSoC4 Cortex-M0 Experience Contest! [/url][/size][/font] [b][font=微软雅黑][size=3][color=Red]Notice on No...; EEWORLD社区 MCU

Audio Issues CETK Test: Today I used cetk to test the AUDIO part of my driver. My audio part is recording and playing sound well. I usually test it on the machine without any problem. . . It has been used for a long time, at...; widb Embedded System

Please help me find out what circuit this is.: [backcolor=rgb(239, 245, 249)]I don't understand how these two transistors are connected, how to analyze, and how the current flows. Please give me some advice. Thank you very much [/backcolor]...; pqa Automotive Electronics

Craftsman's Notes: The Practice and Thinking of a MCU Worker: Online blog, a good book...; songrock MCU

What are the basic structures of DSP chips?: [color=#333333][font=arial, helvetica, sans-serif]The basic structure of DSP chip includes: (1) Harvard structure; (2) pipeline operation; (3) dedicated hardware multiplier; (4) special DSP instructio...; Jacktang DSP and ARM Processors

Here comes the prize: Tektronix Bluetooth headset: The courier called and said something had arrived. I thought it was the prize for the event. When I got it, it turned out to be a Bluetooth headset. The prize was a customized version of the Aigo Blue...; shihuntaotie Integrated technical exchanges

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components

Popular Articles

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews

Index Files: 1994 2831 2160 2503 2022 41 57 44 51 43

Datasheet 0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190

Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号京ICP备10001474号-1 电信业务审批[2006]字第258号函

京公网安备 11010802033920号