S29CD016J1JDGH117 datasheet, PDF

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S29CD016J1JDGH117: DescriptionFlash, 512KX32, 54ns, DIE-74; Categorystorage storage; File Size462KB，16 Pages; ManufacturerCypress Semiconductor

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S29CD016J1JDGH117 Overview

Flash, 512KX32, 54ns, DIE-74

S29CD016J1JDGH117 Parametric

Parameter Name	Attribute value
Maker	Cypress Semiconductor
package instruction	DIE,
Reach Compliance Code	compliant
ECCN code	3A001.A.2.A
Maximum access time	54 ns
Other features	SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE; BOTTOM BOOT BLOCK
startup block	BOTTOM
JESD-30 code	R-XUUC-N74
memory density	16777216 bit
Memory IC Type	FLASH
memory width	32
Number of functions	1
Number of terminals	74
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	145 °C
Minimum operating temperature	-40 °C
organize	512KX32
Package body material	UNSPECIFIED
encapsulated code	DIE
Package shape	RECTANGULAR
Package form	UNCASED CHIP
Parallel/Serial	PARALLEL
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum supply voltage (Vsup)	2.75 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	2.6 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	NO LEAD
Terminal location	UPPER
type	NOR TYPE

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S29CD016J/S29CL016J

Known Good Die

16 Megabit (512k x 32-Bit) CMOS 2.6 or 3.3 Volt-only

Burst Mode, Dual Boot, Simultaneous Read/Write

Flash Memory with VersatileI/O

™

Supplement

(Preliminary)

General Description

The Spansion S29CD016J and S29CL016J devices are Floating Gate products fabricated in 110 nm process technology.

These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two

separate banks. These products can operate up to 56 MHz and use a single V

of 2.5 V to 2.75 V (S29CD-J) or 3.0 V to 3.6 V

(S29CL-J) that make them ideal for today’s demanding automotive applications.

Distinctive Characteristics

Single 2.6 V (S29CD-J) or 3.3 V (S29CL-J) for read/program/

erase

110 nm Floating Gate Technology

Simultaneous Read/Write operation with zero latency

x32 Data Bus

Dual Boot Sector Configuration (top and bottom)

Flexible Sector Architecture

– CD016J & CL016J: Eight 2K Double word, Thirty-two 16K Double

word, and Eight 2K Double Word sectors

Cycling Endurance: 1,000,000 write cycles per sector

(typical)

Command set compatible with JECEC (JC42.4) standard

Supports Common Flash Interface (CFI)

Persistent and Password methods of Advanced Sector

Protection

Unlock Bypass program command to reduce programming

time

Write operation status bits indicate program and erase

operation completion

Hardware (WP#) protection of two outermost sectors in the

large bank

Ready/Busy (RY/BY#) output indicates data available to

system

Suspend and Resume commands for Program and Erase

Operation

VersatileI/O™ control (1.65 V to V

)

Programmable Burst Interface

– Linear for 2, 4, and 8 double word burst with wrap around

Secured Silicon Sector that can be either factory or customer

locked

20 year data retention (typical)

Performance Characteristics

Read Access Times

Speed Option (MHz)

Max Asynch. Access Time, ns (t

ACC

)

Max Synch. Latency, ns (t

IACC

)

Max Synch. Burst Access, ns (t

BACC

)

Max CE# Access Time, ns (t

)

Max OE# Access time, ns (t

)

Typical Program and Erase Times

Double Word Programming

Sector Erase

18 µs

1.0 s

Current Consumption (Max values)

Continuous Burst Read @ 56 MHz

Program

Erase

Standby Mode

90 mA

50 mA

60 µA

Publication Number

S29CD016J-CL016J_KGD_SP

Revision

Amendment

Issue Date

March 9, 2009

This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-

ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document

may be revised by subsequent versions or modifications due to changes in technical specifications.

Supplement

(Preliminar y)

Table of Contents

General Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Distinctive Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Performance Characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

S29CD/CL016J Features.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Die Photograph.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Die Pad Locations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pad Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.1

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Packaging Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1

Surftape Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.2

Waffle Pack Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Product Test Flow.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Absolute Maximum Ratings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operating Ranges

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Physical Specifications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Manufacturing Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Special Handling Instructions.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11.1 Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11.2 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DC Characteristics for KGD Devices at 145°C.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Terms and Conditions of Sale for Spansion Non-Volatile Memory Die.

. . . . . . . . . . . . . . . . . . . . 14

Revision Summary

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10.

11.

12.

13.

14.

List of Figures

Figure 6.1

Figure 7.1

Figure 7.2

Spansion KGD Product Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

List of Tables

Table 3.1

Table 12.1

Pads Relative To Die Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

DC Characteristics, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

S29CD016J/S29CL016J Known Good Die

Revision A3 March 9, 2009

Supplement

(Pre limina r y)

S29CD/CL016J Features

The S29CD016J & S29CL016J Flash devices are burst mode, dual boot, simultaneous read/write Flash

memories with VersatileI/O™ manufactured on 110 nm process technology.

The S29CD016J is a 16 megabit, 2.6 volt-only, single-power-supply, burst mode Flash memory device that

can be configured for 524,288 double words. The S29CL016J is the 3.3 volt-only version of that device. Both

devices can be programmed in standard EPROM programmers.

To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output

enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst

Address Valid (ADV#), and Clock (CLK).

Each device requires only a single 2.6 volt-only (2.50 V – 2.75 V) or 3.3 volt-only (3.00 V – 3.60 V) for both

read and write functions. A 12.0-volt V

is not required for program or erase operations, although an

acceleration pin is available if faster programming performance is required.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The

software command set is compatible with the command sets of the 5 V Am29F and 3 V Am29LV Flash

families. Commands are written to the command register using standard micro-processor write timing.

circuitry. Write cycles also internally latch addresses and data needed for the programming and erase

operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

The

Unlock Bypass

mode facilitates faster programming times by requiring only two write cycles to program

data instead of four.

The

Simultaneous Read/Write architecture

provides simultaneous operation by dividing the memory space

into two banks. The device can begin programming or erasing in one bank, and then simultaneously read

from the other bank, with zero latency. This releases the system from waiting for the completion of program or

erase operations.

The device provides a 256-byte

Secured Silicon Sector

with an one-time-programmable (OTP) mechanism.

In addition, the device features several levels of sector protection, which can disable both the program and

erase operations in certain sectors or sector groups:

Persistent Sector Protection

is a command sector

protection method that replaces the old 12 V controlled protection method;

Password Sector Protection

is a

highly sophisticated protection method that requires a password before changes to certain sectors or sector

groups are permitted;

WP# Hardware Protection

prevents program or erase in the two outermost 8 Kbytes

sectors of the larger bank.

The device defaults to the Persistent Sector Protection mode. The customer must then choose if the

Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always

available, independent of the other protection method chosen.

The

VersatileI/O™ (V

)

feature allows the output voltage generated on the device to be determined based

on the V

ΙΟ

level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving

signals to and from other 1.8 V devices on the same bus.

The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,

by reading the DQ7 (Data# Polling), or DQ6 (toggle)

status bits.

After a program or erase cycle has been

completed, the device is ready to read array data or accept another command.

The

sector erase architecture

allows memory sectors to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection

measures include a low V

detector that automatically inhibits write operations

during power transitions. The

password and software sector protection

feature disables both program and

erase operations in any combination of sectors of memory. This can be achieved in-system at V

level.

The

Program/Erase Suspend/Erase Resume

feature enables the user to put erase on hold for any period of

time to read data from, or program data to, any sector that is not selected for erasure. True background erase

can thus be achieved.

The

hardware RESET# pin

terminates any operation in progress and resets the internal state machine to

reading array data.

March 9, 2009 Revision A3

S29CD016J/S29CL016J Known Good Die

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