74HCT04
Hex Inverter
With LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
The 74HCT04 may be used as a level converter for interfacing TTL
or NMOS outputs to High−Speed CMOS inputs. The HCT04A is
identical in pinout to the LS04.
Features
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MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
HCT04G
AWLYWW
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
mA
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 48 FETs or 12 Equivalent Gates
These are Pb−Free Devices
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCT04
A
L, WL
Y
W, WW
G or
G
HCT
04
ALYWG
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 1
1
Publication Order Number:
74HCT04/D
74HCT04
Pinout: 14−Lead Packages
(Top View)
V
CC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
A1
LOGIC DIAGRAM
1
2
Y1
A2
3
4
Y2
A3
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
A4
5
6
Y3
9
8
Y4
A5
11
10
Y5
FUNCTION TABLE
Inputs
A
L
H
Outputs
Y
H
L
Y=A
Pin 14 = V
CC
Pin 7 = GND
A6
13
12
Y6
ORDERING INFORMATION
Device
74HCT04DR2G
74HCT04DTR2G
Package
SOIC−14
(Pb−Free)
TSSOP−14*
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HCT04
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
260
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
– 65 to + 150
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
Min
4.5
0
– 55
0
Max
5.5
V
CC
+ 125
500
Unit
V
V
_C
ns
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output
Voltage
Condition
V
out
= 0.1V
|I
out
|
≤
20mA
V
out
= V
CC
−
0.1V
|I
out
|
≤
20mA
V
in
= V
IL
|I
out
|
≤
20mA
V
in
= V
IL
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
|
≤
20mA
V
in
= V
IH
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
Additional Quiescent Supply
Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
|I
out
|
≤
4.0mA
|I
out
|
≤
4.0mA
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
Guaranteed Limit
−55
to 25°C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
2.0
≤85°C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
20
≤125°C
2.0
2.0
0.8
0.8
4.4
5.4
3.70
0.1
0.1
0.40
±1.0
40
mA
mA
V
Unit
V
V
V
DI
CC
≥
−55°C
5.5
2.9
25 to 125°C
2.4
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I
CC
+
ΣDI
CC
.
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3
74HCT04
AC CHARACTERISTICS
(V
CC
= 5.0V
±10%,
C
L
= 50pF, Input t
r
= t
f
= 6ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
TLH
,
t
THL
C
in
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Maximum Input Capacitance
−55
to 25°C
15
17
15
10
≤85°C
19
21
19
10
≤125°C
22
26
22
10
Unit
ns
ns
pF
3. For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Inverter)*
22
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
t
f
INPUT A
2.7V
1.3V
0.3V
t
PLH
90%
OUTPUT Y
t
TLH
1.3V
10%
t
r
3.0V
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
GND
t
PHL
t
THL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
A
Y
Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)
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4
74HCT04
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
−A−
14
8
−B−
P
7 PL
0.25 (0.010)
M
B
M
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
G
C
−T−
SEATING
PLANE
R
X 45
_
F
D
14 PL
0.25 (0.010)
K
M
M
S
J
T B
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
_
7
_
0.228 0.244
0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
1
0.58
14X
14X
1.52
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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