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CY7C144, CY7C145
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
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■
■
■
■
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Functional Description
The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and
8K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C144/5 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5 can
be used as a standalone 64/72-Kbit dual-port static RAM or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S pin
is provided for implementing 16/18-bit or wider memory applica-
tions without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor
designs,
communications
status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags, BUSY
and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a mail box. The
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
R/W
R
CE
R
OE
R
True Dual-Ported Memory Cells that Enable Simultaneous
Reads of the same Memory Location
8K x 8 Organization (CY7C144)
8K x 9 Organization (CY7C145)
0.65-Micron CMOS for optimum Speed and Power
High Speed Access: 15 ns
Low Operating Power: I
CC
= 160 mA (max.)
Fully Asynchronous Operation
Automatic Power Down
TTL Compatible
Master/Slave Select Pin enables Bus Width Expansion to 16/18
Bits or more
Busy Arbitration Scheme provided
Semaphores included to permit Software Handshaking
between Ports
INT Flag for Port-to-Port Communication
Available in 68-pin PLCC, 64-pin and 80-pin TQFP
Pb-free Packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
(7C145) I/O
8L
I/O
7L
I/O
0L
BUSY
L
I/O
CONTROL
I/O
CONTROL
I/O
8R
(7C145)
I/O
7R
I/O
0R
BUSY
R
[1, 2]
A
12R
[1, 2]
A
12L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L
[2]
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
R
INT
R
[2]
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 26, 2009
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CY7C144, CY7C145
Architecture
The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes or reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT) pins can be used
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the CY7C144/5 can function as a Master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The CY7C144/5
has an automatic power down feature controlled by CE. Each
port is provided with its own output enable control (OE), which
allows data to be read from the device.
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This enables the device to interface to a master device with no
external components.Writing of slave devices must be delayed
until after the BUSY input has settled. Otherwise, the slave chip
may begin a write cycle during a contention situation.When
presented a HIGH input, the M/S pin allows the device to be used
as a master and therefore the BUSY line is an output. BUSY can
then be used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for t
SOP
before attempting to read the semaphore.
The semaphore value is available t
SWRD
+ t
DOE
after the rising
edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control over the shared resource,
otherwise (reads a 1) it assumes the right port has control and
continues to poll the semaphore.When the right side has relin-
quished control of the semaphore (by writing a 1), the left side
will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a 1 is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A
0–2
represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access.When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
0
is used. If a 0 is written
to the left port of an unused semaphore, a 1 appears at the same
semaphore address on the right port. That semaphore can now
only be modified by the side showing 0 (the left port in this case).
If the left port now relinquishes control by writing a 1 to the
semaphore, the semaphore will be set to 1 for both sides.
However, if the right port had requested the semaphore (written
a 0) while the left port had control, the right port would immedi-
ately own the semaphore as soon as the left port released it.
Table 5
shows sample semaphore operations.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
SPS
of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power up. All Semaphores on
both sides should have a one written into them at initialization
from both sides to assure that they are free when needed.
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the OE pin (see
Figure 8
on page 11) or the R/W pin
(see Write Cycle No. 2 waveform). Data can be written to the
device t
HZOE
after the OE is deasserted or t
HZWE
after the falling
edge of R/W. Required inputs for non-contention operations are
summarized in
Table 3.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available t
ACE
after CE or t
DOE
after OE are
asserted. If the user of the CY7C144/5 wishes to access a
semaphore flag, then the SEM pin must be asserted instead of
the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INT
R
) is set. This flag is cleared when the right port
reads that same location. Setting the left port’s interrupt flag
(INT
L
) is accomplished when the right port writes to location
1FFE. This flag is cleared when the left port reads location 1FFE.
The message at 1FFF or 1FFE is user-defined. See
Table 4
for
input requirements for INT. INT
R
and INT
L
are push-pull outputs
and do not require pull-up resistors to operate.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simulta-
neous memory location access (contention). If both ports’ CEs
are asserted and an address match occurs within t
PS
of each
other the Busy logic determines which port has access. If t
PS
is
violated, one port will definitely gain permission to the location,
but it is not guaranteed which one. BUSY will be asserted t
BLA
after an address match or t
BLC
after CE is taken LOW. BUSY
L
and BUSY
R
in master mode are push-pull outputs and do not
require pull-up resistors to operate.
Document #: 38-06034 Rev. *E
Page 4 of 20
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