CAT28LV64JI-30T datasheet, PDF

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CAT28LV64JI-30T: DescriptionIC 8K X 8 EEPROM 3V, 300 ns, PDSO28, SOIC-28, Programmable ROM; Categorystorage storage; File Size146KB，15 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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CAT28LV64JI-30T Overview

IC 8K X 8 EEPROM 3V, 300 ns, PDSO28, SOIC-28, Programmable ROM

CAT28LV64JI-30T Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	SOP,
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	300 ns
Other features	100000 PROGRAM/ERASE CYCLES; 100 YEAR DATA RETENTION
Data retention time - minimum	100
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	17.9 mm
memory density	65536 bit
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	28
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
Maximum write cycle time (tWC)	5 ms

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CAT28LV64

64 kb CMOS Parallel

EEPROM

Description

The CAT28LV64 is a low voltage, low power, CMOS Parallel

EEPROM organized as 8K x 8−bits. It requires a simple interface for

in−system programming. On−chip address and data latches,

self−timed write cycle with auto−clear and V

power up/down write

protection eliminate additional timing and protection hardware. DATA

Polling and Toggle status bit signal the start and end of the self−timed

write cycle. Additionally, the CAT28LV64 features hardware and

software write protection.

The CAT28LV64 is manufactured using ON Semiconductor’s

advanced CMOS floating gate technology. It is designed to endure

100,000 program/erase cycles and has a data retention of 100 years.

The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP,

28−pin SOIC or 32−pin PLCC packages.

Features

http://onsemi.com

PDIP−28

P, L SUFFIX

CASE 646AE

SOIC−28

J, K, W, X SUFFIX

CASE 751BM

•

3.0 V to 3.6 V Supply

•

Read Access Times:

•

– 150/200/250 ns

Low Power CMOS Dissipation:

– Active: 8 mA Max.

– Standby: 100

Max.

Simple Write Operation:

– On−chip Address and Data Latches

– Self−timed Write Cycle with Auto−clear

Fast Write Cycle Time:

– 5 ms Max.

Commercial, Industrial and Automotive Temperature Ranges

CMOS and TTL Compatible I/O

Automatic Page Write Operation:

– 1 to 32 bytes in 5 ms

– Page Load Timer

End of Write Detection:

– Toggle bit

– DATA Polling

Hardware and Software Write Protection

100,000 Program/Erase Cycles

100 Year Data Retention

These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

PLCC−32

N, G SUFFIX

CASE 776AK

TSOP−28

H13 SUFFIX

CASE 318AE

PIN FUNCTION

Pin Name

−A

I/O

−I/O

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

Output Enable

Write Enable

3.0 V to 3.6 V Supply

Ground

No Connect

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 15 of this data sheet.

Semiconductor Components Industries, LLC, 2009

October, 2009

−

Rev. 7

Publication Order Number:

CAT28LV64/D

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