PLC42VA12A datasheet, PDF - EEWORLD Datasheet

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PLC42VA12A: DescriptionOT PLD, 55ns, PQCC28, 0.450 INCH, PLASTIC, LCC-28; CategoryProgrammable logic devices Programmable logic; File Size212KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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PLC42VA12A Overview

OT PLD, 55ns, PQCC28, 0.450 INCH, PLASTIC, LCC-28

PLC42VA12A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	QLCC
package instruction	QCCJ, LDCC28,.5SQ
Contacts	28
Reach Compliance Code	unknown
Other features	PROGRAMMABLE MULTI-FUNCTION PLD; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; REGISTER PRELOAD
Architecture	PLS-TYPE
maximum clock frequency	14.9 MHz
JESD-30 code	S-PQCC-J28
length	11.505 mm
Humidity sensitivity level	1
Dedicated input times	8
Number of I/O lines	12
Number of entries	42
Output times	12
Number of product terms	105
Number of terminals	28
Maximum operating temperature	75 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Programmable logic type	OT PLD
propagation delay	55 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.505 mm

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Philips Semiconductors Programmable Logic Devices

Product specification

CMOS programmable multi-function PLD

(42

105

12)

PLC42VA12

DESCRIPTION

The new PLC42VA12 CMOS PLD from

Philips Semiconductors exhibits a unique

combination of the two architectural concepts

that revolutionized the PLD marketplace.

The Philips Semiconductors unique Output

Macro Cell (OMC) embodies all the

advantages and none of the disadvantages

associated with the “V” type Output Macro

Cell devices. This new design, combined with

added functionality of two programmable

arrays, represents a significant advancement

in the configurability and efficiency of

multi-function PLDs.

The most significant improvement in the

Output Macro Cell structure is the

implementation of the register bypass

function. Any of the 10 J-K/D registers can be

individually bypassed, thus creating a

combinatorial I/O path from the AND array to

the output pin. Unlike other “V” type devices,

the register in the PLC42VA12 Macro Cell

remains fully functional as a buried register.

Both the combinatorial I/O and buried register

have separate input paths (from the AND

array). In most V-type architectures, the

configured as a combinatorial I/O. This

feature provides the capability to operate the

buried register independently from the

combinatorial I/O.

The PLC42VA12 is an EPROM-based CMOS

device. Designs can be generated using

Philips Semiconductors SNAP PLD design

software packages or one of several other

commercially available JEDEC standard PLD

design software packages.

FEATURES

•

High-speed EPROM-based CMOS

Multi-Function PLD

–

Super set of 22V10, 32VX10 and

20RA10 PAL® ICs

PIN CONFIGURATIONS

FA and N Pack-

ages

I0/CLK

24 V

23 M9

22 M8

21 M7

20 M6

19 M5

18 M4

17 M3

16 M2

15 M1

14 M0

13 I9/OE

•

Two fully programmable arrays eliminate

“P-term Depletion”

–

Up to 64 P-terms per OR function

•

Improved Output Macro Cell Structure

–

Individually programmable as:

* Registered Output with feedback

* Registered Input

* Combinatorial I/O with Buried Register

* Dedicated I/O with feedback

* Dedicated Input (combinatorial)

–

Bypassed Registers are 100% functional

with separate input and feedback paths

–

Individual Output Enable control

functions

* From pin or AND array

B0 10

B1 11

GND 12

•

Reprogrammable – 100% tested for

programmability

N = Plastic DIP (300mil-wide)

FA = Ceramic DIP with Quartz Window (300mil-wide)

•

Eleven clock sources

•

Features

A Package

I0/

I1 CLK N/C V

M9 M8

25 M7

24 M6

23 M5

22 N/C

21 M4

20 M3

19 M2

•

Security fuse

APPLICATIONS

–

Synchronous

–

Asynchronous

N/C

•

Mealy or Moore State Machines

•

Multiple, independent State Machines

•

10-bit ripple cascade

•

Sequence recognition

•

Bus Protocol generation

•

Industrial control

•

A/D Scanning

I7 10

I8 11

B0 B1 GND N/C I9/ M0 M1

A = Plastic Leaded Chip Carrier (450mil-square)

ORDERING INFORMATION

DESCRIPTION

24-Pin Ceramic Dual In-Line with window,

Reprogrammable (300mil-wide)

24-Pin Plastic Dual In-Line,

One Time Programmable (300mil-wide)

28-Pin Plastic Leaded Chip Carrier,

One Time Programmable (450mil-wide)

ORDER CODE

PLC42VA12FA

PLC42VA12N

PLC42VA12A

DRAWING NUMBER

1478A

0410D

0401F

PAL is a registered trademark of Advanced Micro Devices, Inc.

October 22, 1993

853–1414 11164

PLC42VA12A Related Products

	PLC42VA12A	PLC42VA12N	PLC42VA12FA
Description	OT PLD, 55ns, PQCC28, 0.450 INCH, PLASTIC, LCC-28	OT PLD, 55ns, PDIP24, 0.300 INCH, PLASTIC, DIP-24	UV PLD, 55ns, CDIP24, 0.300 INCH, CERAMIC, DIP-24
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	NXP	NXP	NXP
Parts packaging code	QLCC	DIP	DIP
package instruction	QCCJ, LDCC28,.5SQ	DIP, DIP24,.3	DIP, DIP24,.3
Contacts	28	24	24
Reach Compliance Code	unknown	unknown	unknown
Other features	PROGRAMMABLE MULTI-FUNCTION PLD; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; REGISTER PRELOAD	PROGRAMMABLE MULTI-FUNCTION PLD; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; REGISTER PRELOAD	PROGRAMMABLE MULTI-FUNCTION PLD; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; REGISTER PRELOAD
Architecture	PLS-TYPE	PLS-TYPE	PLS-TYPE
maximum clock frequency	14.9 MHz	14.9 MHz	14.9 MHz
JESD-30 code	S-PQCC-J28	R-PDIP-T24	R-GDIP-T24
Humidity sensitivity level	1	1	1
Dedicated input times	8	8	8
Number of I/O lines	12	12	12
Number of entries	42	42	42
Output times	12	12	12
Number of product terms	105	105	105
Number of terminals	28	24	24
Maximum operating temperature	75 °C	75 °C	75 °C
organize	8 DEDICATED INPUTS, 12 I/O	8 DEDICATED INPUTS, 12 I/O	8 DEDICATED INPUTS, 12 I/O
Output function	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
encapsulated code	QCCJ	DIP	DIP
Encapsulate equivalent code	LDCC28,.5SQ	DIP24,.3	DIP24,.3
Package shape	SQUARE	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	225	225	225
power supply	5 V	5 V	5 V
Programmable logic type	OT PLD	OT PLD	UV PLD
propagation delay	55 ns	55 ns	55 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	YES	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED	COMMERCIAL EXTENDED
Terminal form	J BEND	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	2.54 mm
Terminal location	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
length	11.505 mm	31.7 mm	-
Maximum seat height	4.57 mm	4.7 mm	-
width	11.505 mm	7.62 mm	-

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