Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
PHP130N03LT, PHB130N03LT
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 30 V
I
D
= 75 A
g
s
R
DS(ON)
≤
6 mΩ (V
GS
= 5 V)
R
DS(ON)
≤
5 mΩ (V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB130N03LT is supplied in the SOT404 surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
drain
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C; V
GS
= 5 V
T
mb
= 100 ˚C; V
GS
= 5 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
13
75
75
240
187
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin 2 of the SOT404 package.
January 1998
1
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
ESD LIMITING VALUE
SYMBOL PARAMETER
V
C
Electrostatic discharge
capacitor voltage, all pins
CONDITIONS
PHP130N03LT, PHB130N03LT
MIN.
-
MAX.
2
UNIT
kV
Human body model (100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
SOT78 package, in free air
SOT404 package, pcb mounted, minimum
footprint
-
-
TYP. MAX. UNIT
-
60
50
0.8
-
-
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
(BR)GSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
I
G
= 1 mA
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 5 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 25 A; T
j
= 175˚C
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
Gate-source leakage current V
GS
=
±5
V; V
DS
= 0 V;
T
j
= 175˚C
Zero gate voltage drain
V
DS
= 30 V; V
GS
= 0 V;
current
T
j
= 175˚C
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 75 A; V
DD
= 24 V; V
GS
= 5 V
MIN.
30
27
10
1
0.5
-
-
-
-
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
-
1.5
-
-
5
4.5
-
40
0.02
-
0.05
-
92
10
36
45
120
225
100
3.5
4.5
7.5
5000
1150
500
-
-
-
2
-
2.3
6
5
11
-
1
10
10
500
-
-
-
60
170
300
135
-
-
-
-
-
-
V
V
V
V
V
V
mΩ
mΩ
mΩ
S
µA
µA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
V
DD
= 15 V; I
D
= 25 A;
V
GS
= 5 V; R
G
= 5
Ω
Resistive load
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
January 1998
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP130N03LT, PHB130N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 75 A; V
GS
= 0 V
I
F
= 75 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 25 V
-
-
-
-
TYP. MAX. UNIT
-
-
0.85
1.0
100
0.6
75
240
1.2
-
-
-
A
A
V
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
CONDITIONS
MIN.
-
MAX.
500
UNIT
mJ
Drain-source non-repetitive I
D
= 75 A; V
DD
≤
15 V;
unclamped inductive turn-off V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
energy
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
ID (A)
140
120
100
80
60
40
20
Current Derating
Limited by package
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
0
20
40
60
80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
January 1998
3
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP130N03LT, PHB130N03LT
1000
Drain current, ID (A)
ID
S/
7506-30
RDS(ON) / mOhm
10
3
9506-30
100
RD
N
S(O
)=
VD
8
tp = 10 us
100 us
DC
1 ms
10 ms
100 ms
3.5
4
5
6
6
4
2
10
1
1
10
Drain-source voltage, VDS (V)
100
0
0
20
40
ID / A
60
80
100
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Zth / (K/W)
1E+00
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
ID / A
100
9506-30
0.5
1E-01
0.2
0.1
0.05
1E-02
0.02
0
1E-03
1E-07
80
60
Tj / C = 175
25
P
D
t
p
t
p
D=
T
T
t
40
20
1E-05
1E-03
t/s
1E-01
1E+01
0
0
1
2
VGS / V
3
4
5
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
ID / A
6
3.5
5
3
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
gfs / S
100
BUK9506-30
100
9506-30
80
80
60
VGS / V =
2.8
60
Tj / C = 25
40
2.6
2.4
2.2
40
175
20
20
0
0
2
4
VDS / V
6
8
10
0
0
20
40
ID / A
60
80
100
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
January 1998
4
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
PHP130N03LT, PHB130N03LT
a
2
30V TrenchMOS
10000
C / pF
9506-30
Ciss
1.5
1
1000
Coss
Crss
0.5
0
-100
-50
0
50
Tj / C
100
150
200
100
0.1
1
VDS / V
10
100
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
VGS(TO) / V
max.
2
typ.
1.5
min.
1
BUK959-60
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
VGS / V
2.5
5
9506-30
4
VDS / V = 6
3
24
2
0.5
1
0
-100
-50
0
50
Tj / C
100
150
200
0
0
20
40
QG / nC
60
80
100
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 75 A; parameter V
DS
IF / A
1E-01
100
9506-30
1E-02
2%
typ
98%
80
1E-03
60
Tj / C = 175
40
25
1E-04
20
1E-05
0
0
0.5
1
VSDS / V
1.5
2
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
January 1998
5
Rev 1.300
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