MX29F100T/B
1M-BIT [128Kx8/64Kx16] CMOS FLASH MEMORY
FEATURES
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5V±10% for read, erase and write operation
131072x8/ 65536x16 switchable
Fast access time:90/120ns
Low power consumption
- 40mA maximum active current(5MHz)
- 1
uA
typical standby current
Command register architecture
- Byte/ Word Programming (7us/ 12us typical)
- Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and
64K-Byte x1)
Auto Erase (chip) and Auto Program
- Automatically erase any combination of sectors or
with Erase Suspend capability.
- Automatically program and verify data at specified
address
Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
- Superior inadvertent write protection
Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/
12V system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 44-pin SOP
- 48-pin TSOP
Ready/Busy pin(RY/BY)
- Provides a hardware method or detecting program
or erase cycle completion
Erase suspend/ Erase Resume
- Suspend an erase operation to read data from, or
program data to a sector that is not being erased,
then resume the erase operation.
Hardware RESET pin
- Hardware method of resetting the device to reading
the device to reading array data.
20 years data retention
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GENERAL DESCRIPTION
The MX29F100T/B is a 1-mega bit Flash memory
organized as 131,072 bytes or 65,536 words.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29F100T/B is packaged in 44-pin
SOP and 48-pin TSOP. It is designed to be repro-
grammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F100T/B offers access time 90ns.
To eliminate bus contention, the MX29F100T/B has
separate chip enable (CE) and output enable (OE)
controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F100T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs and
fixed power supply levels during erase and
P/N:PM0548
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The
MX29F100T/B uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
REV. 1.4, DEC. 29, 2003
1
MX29F100T/B
PIN CONFIGURATIONS
44SOP(500mil)
NC
RY/BY
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
NC
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
48 TSOP(TYPE I) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
MX29F100T/B
MX29F100T/B
(NORMAL TYPE)
PIN DESCRIPTION:
SYMBOL
A0-A15
Q0-Q14
Q15/A-1
CE
OE
RESET
WE
RY/BY
BYTE
VCC
GND
NC
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr.(Byte mode)
Chip Enable Input
Output Enable Input
Hardware Reset Pin, Active low
Write Enable Input
Ready/Busy Output
Word/Byte Selection Input
Power Supply Pin (+5V)
Ground Pin
Pin Not Connected Internally
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REV. 1.4, DEC. 29, 2003
2
MX29F100T/B
SECTOR STRUCTURE
MX29F100T Top Boot Sector Addresses Tables
A15
0
1
1
1
1
A14
X
0
1
1
1
A13
X
X
0
0
1
A12
X
X
0
1
X
(x8)Address Range
00000h-0FFFFh
64KB
10000h-17FFFh
32KB
18000h-19FFFh
8KB
1A000h-1BFFFh
8KB
1C000h-1FFFFh
16KB
(x16) Address Range
00000h-07FFFh
32KW
08000h-0BFFFh
16KW
0C000h-0CFFFh
4KW
0D000h-0DFFFh
4KW
0E000h-0FFFFh
8KW
SA0
SA1
SA2
SA3
SA4
MX29F100B Bottom Boot Sector Addresses Tables
A15
0
0
0
0
1
A14
0
0
0
1
X
A13
0
1
1
X
X
A12
X
0
1
X
X
(x8)Address Range
00000h-03FFFh
16KB
04000h-05FFFh
8KB
06000h-07FFFh
8KB
08000h-0FFFFh
32KB
10000h-1FFFFh
64KB
(x16) Address Range
00000h-01FFFh
8KW
02000h-02FFFh
4KW
03000h-03FFFh
4KW
04000h-07FFFh
16KW
08000h-0FFFFh
32KW
SA0
SA1
SA2
SA3
SA4
P/N:PM0548
REV. 1.4, DEC. 29, 2003
3
MX29F100T/B
SECTOR DIAGRAM
WRITE
CE
OE
WE
CONTROL
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
PROGRAM/ERASE
STATE
X-DECODER
MX29F100T/B
FLASH
ARRAY
ARRAY
STATE
REGISTER
ADDRESS
LATCH
A0-A15
AND
BUFFER
SENSE
AMPLIFIER
A-1/Q15
Y-DECODER
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
I/O BUFFER
Q0~Q14
P/N:PM0548
REV. 1.4, DEC. 29, 2003
4
MX29F100T/B
AUTOMATIC PROGRAMMING
The MX29F100T/B is byte/ word programmable using
the Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out sequence or verify the data programmed. The
typical chip programming time of the MX29F100T/B at
room temperature is less than 3.5 seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, verifies the erase and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the
status of the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29F100T/B electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron
injection.
During a program cycle, the state-machine will control the
program sequences and command register will not re-
spond to any command set. During a Sector Erase cycle,
the command register will only respond to Erase Sus-
pend command. After Erase Suspend is complete, the
device stays in read mode. After the state machine has
completed its task, it will allow the command register to
respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase
pulses according to MXIC's Automatic Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than 3 seconds. The Automatic
Erase algorithm automatically programs the entire
array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
by the device.
AUTOMATIC SECTOR ERASE
The MX29F100T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally controlled by the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires
the user to only write program set-up commands
(include 2 unlock write cycle and A0H) and a program
command (program data and address). The device
automatically times the programming pulse width,
verifies the program and counts the number of
sequences. A status bit similar to DATA polling and a
status bit toggling between consecutive read cycles,
provides feedback to the user as to the status of the
programming operation.
P/N:PM0548
REV. 1.4, DEC. 29, 2003
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